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product specification main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 1 of 104 june 2004 nrf9e5 433/868/915mhz rf transceiver with embedded 8051 compatible microcontroller and 4 input, 10 bit adc features nrf905 433/868/915 mhz transceiver 8051 compatible microcontroller applications sports and leisure equipment 4 input, 10bit 80ksps adc single 1.9v to 3.6v supply alarm and security system small 32 pin qfn (5x5 mm) package industrial sensors extremely low cost bill of material (bom) remote control internal vdd monitoring surveillance 2.5 m a standby with wakeup on timer or external pin automotive adjustable output power up to 10dbm telemetry channel switching time less than 650 m s keyless entry low tx supply current, typical 11ma @-10dbm toys low rx supply current typical 12.5ma peak low mcu supply current, typ. 1ma at 4mhz @3volt suitable for frequency hopping carrier detect for ?listen before transmit protocol? general description nrf9e5 is a true single chip system with fully integrated rf transceiver, 8051 compatible microcontroller and a 4 input 10bit 80ksps ad converter. the transceiver of the system supports all the features available in the nrf905 chip including shockburst tm , which automatically handles preamble, address and crc. the circuit has embedded voltage regulators, which provides maximum noise immunity and allows operation on a single 1.9v to 3.6v supply. nrf9e5 is compatible with fcc standard cfr47 part 15 and etsi en 300 220-1. quick reference data parameter value unit minimum supply voltage 1.9 v temperature range -40 to +85 c supply current in transmit @ -10dbm output power 11 ma supply current in receive mode 12.5 ma supply current for m -controller 4mhz @ 3volt 1 ma supply current for adc 0.9 ma maximum transmit output power 10 dbm transmitted data rate (manchester-encoder embedded) 100 kbps sensitivity -100 dbm supply current in power down mode 2.5 m a table 1 nrf9e5 quick reference data.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 2 of 104 june 2004 ordering information type number description version nrf9e5 ic 32l qfn 5x5 mm - nrf9e5-evkit 433 evaluation kit 433mhz 1.0 nrf9e5-evkit 868/915 evaluation kit 868/915mhz 1.0 table 2 nrf9e5 ordering information. block diagram vdd_pa (19) ain0 (29) ain1 (28) ain2 (27) ain3 (26) aref (30) iref (23) a/d converter cpu 8051 compatible microcontroller timer 2 timer 1 timer 0 uart0 7-channel interrupt 4k byte ram boot loader 256 byte ram nrf905 433/868/ 915 mhz radio tranceiver xtal oscillator bias rtc timer watch- dog spi pwm low power rc oscillator port logic power mgmt reset regulators miso (11) mosi (10) sck (12) eecsn (13) xc1 (14) xc2 (15) vdd (4) vdd (17) vdd (25) vss (16) vss (18) vss (22) vss (24) dvdd_1v2 (31) vss (5) p00 (32) p01 (1) p02 (2) p03 (3) p04 (6) p05 (7) p06 (8) p07 (9) ant2 (21) ant1 (20) 25320 eeprom sdo sdi csn sck 8. ch programmable wakeup figure 1 nrf9e5 block diagram.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 3 of 104 june 2004 table of contents 1 architectural overview ................................ ................................ ................................ . 5 1.1 microcontroller ................................ ................................ ................................ ......... 5 1.2 pwm ................................ ................................ ................................ ....................... 6 1.3 spi ................................ ................................ ................................ .......................... 6 1.4 port logic ................................ ................................ ................................ ................ 6 1.5 power management ................................ ................................ ................................ .. 7 1.6 lf clock, rtc wakeup timer, gpio wakeup and watchdog ................................ .... 7 1.7 xtal oscillator ................................ ................................ ................................ ....... 7 1.8 ad converter ................................ ................................ ................................ .......... 8 1.9 radio transceiver ................................ ................................ ................................ ..... 8 2 eletrical specification ................................ ................................ ................................ ... 9 2.1 detailed current information ................................ ................................ ................... 10 3 pin assignment ................................ ................................ ................................ ........... 11 4 pin function ................................ ................................ ................................ ............... 12 5 system clock ................................ ................................ ................................ ............. 13 6 digital i/o ports ................................ ................................ ................................ ......... 14 6.1 i/o port behavior during reset ................................ ................................ ............ 14 6.2 port 0 (p0) ................................ ................................ ................................ ............. 14 6.3 port 1 (p1 or spi port) ................................ ................................ ............................ 15 7 analog interface ................................ ................................ ................................ ......... 17 7.1 cryst al specification ................................ ................................ ............................... 17 7.2 antenna output ................................ ................................ ................................ ...... 17 7.3 adc inputs ................................ ................................ ................................ ............ 17 7.4 current reference ................................ ................................ ................................ .. 17 7.5 digital power de-coupling ................................ ................................ ..................... 18 8 internal interface ad converter and transceiver ................................ .......................... 19 8.1 p2 - radio general purpose io port ................................ ................................ ......... 19 9 tranceiver subsystem (nrf905) ................................ ................................ .................. 21 9.1 rf modes of operation ................................ ................................ ........................... 21 9.2 nrf shockburst? mode ................................ ................................ ........................ 21 9.3 standby mode ................................ ................................ ................................ ........ 26 9.4 output power adjustment ................................ ................................ ....................... 26 9.5 modulation ................................ ................................ ................................ ............. 26 9.6 output freque ncy ................................ ................................ ................................ ... 27 9.7 carrier detect. ................................ ................................ ................................ ........ 27 9.8 address match ................................ ................................ ................................ ....... 28 9.9 data ready ................................ ................................ ................................ ............ 28 9.10 auto retransmit ................................ ................................ ................................ . 28 9.11 rx reduced po wer mode ................................ ................................ ................... 28 10 ad converter subsystem ................................ ................................ ............................ 29 10.1 ad converter ................................ ................................ ................................ .... 29 10.2 ad converter usage ................................ ................................ .......................... 30 10.3 ad converter sampling and timing ................................ ................................ .... 31 11 tranceiver and ad converter configuration ................................ ................................ 33 11.1 internal spi register configuration ................................ ................................ ...... 33 11.2 spi ? instruction set ................................ ................................ ........................... 35 11.3 spi timing ................................ ................................ ................................ ......... 36 11.4 rf configuration ? register description ................................ .............................. 37 11.5 adc - configuration register description ................................ ........................... 38 11.6 status-register description ................................ ................................ ................. 38 11.7 rf - regist er contents ................................ ................................ ........................ 39
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 4 of 104 june 2004 11.8 adc configuration register contents ................................ ................................ . 40 11.9 adc data register contents ................................ ................................ ............... 40 11.10 status register contents ................................ ................................ ..................... 40 12 tranceive r subsytem timing ................................ ................................ ....................... 41 12.1 device switching times ................................ ................................ ..................... 41 12.2 shockburst tm tx timing ................................ ................................ .................... 41 12.3 shockburst tm rx timing ................................ ................................ .................... 42 13 spi ................................ ................................ ................................ ............................ 43 14 pwm ................................ ................................ ................................ ......................... 44 15 interrupts ................................ ................................ ................................ ................... 45 15.1 interrupt sfrs ................................ ................................ ................................ .... 45 15.2 interrupt processing ................................ ................................ ............................ 48 15.3 interrupt masking ................................ ................................ ............................... 48 15.4 interrupt priorities ................................ ................................ .............................. 48 15.5 interrupt sampling ................................ ................................ .............................. 49 15.6 interrupt latency ................................ ................................ ................................ 50 15.7 interrupt latency from power down state. ................................ .......................... 50 15.8 single-step operation ................................ ................................ ......................... 50 16 lf clock wakeup functions and watchdog ................................ ................................ . 51 16.1 the lf clock ................................ ................................ ................................ ..... 51 16.2 tick calibration ................................ ................................ ................................ .. 51 16.3 rtc wakeup timer ................................ ................................ ............................ 52 16.4 programmable gpio wakeup function ................................ ................................ 52 16.5 watchdog ................................ ................................ ................................ ........... 53 16.6 programming interface to watchdog and wakeup functions ................................ . 53 16.7 reset ................................ ................................ ................................ ................. 55 17 power saving modes ................................ ................................ ................................ .. 57 17.1 standard 8051 power saving modes ................................ ................................ .... 57 17.2 additional power down modes ................................ ................................ ........... 58 18 microcontroller ................................ ................................ ................................ ........... 60 18.1 memory organization ................................ ................................ ......................... 60 18.2 program format in external eeprom ................................ ................................ 61 18.3 instruction set ................................ ................................ ................................ .... 62 18.4 instruction timing ................................ ................................ .............................. 68 18.5 dual data pointers ................................ ................................ .............................. 68 18.6 special function registers ................................ ................................ .................. 69 18.7 sfr registers unique to nrf9e5 ................................ ................................ ........ 73 18.8 timers/counters ................................ ................................ ................................ . 74 18.9 serial interface ................................ ................................ ................................ ... 81 19 package outline ................................ ................................ ................................ .......... 92 20 pcb layout and decoupling guidelines ................................ ................................ ...... 93 21 application examples ................................ ................................ ................................ . 94 21.1 differential connection to a loop anten na ................................ .......................... 94 21.2 pcb layout example, differential connection to a loop antenna ........................ 96 21.3 single ended connection to 50 w antenna ................................ ............................ 97 21.4 pcb layout example, single ended connecti on to 50 w antenna ......................... 99 21.5 configure the chip as nrf905. ................................ ................................ ............ 99 22 absolute maximum ratings ................................ ................................ ....................... 100 23 glossery of terms ................................ ................................ ................................ ..... 101 24 definitions ................................ ................................ ................................ ................ 102 25 your notes ................................ ................................ ................................ ............... 103
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 5 of 104 june 2004 1 architectural overview this section will give a brief overview of each of the blocks in the block diagram in figure 1 . 1.1 microcontroller the nrf9e5 microcontroller is instruction set compatible with the industry standard 8051. instruction timing is slightly different from the industry standard, typically each instruction will use from 4 to 20 clock cycles, compared with 12 to 48 for the ?standard?. the interrupt controller is extended to support 5 additional interrupt sources; adc, spi, 2 for the radio and a wakeup function. there are also 3 timers that are 8052 compatible, plus some extensions, in the microcontroller core. an 8051 compatible uart that can use timer1 or timer2 for baud rate generation in the traditional asynchronous modes is included. the cpu is equipped with 2 data pointers to facilitate easier moving of data in the xram area, which is a common 8051 extension. the microcontroller clock is derived from the crystal oscillator. 1.1.1 memory configuration the microcontroller has a 256-byte data ram (8052 compatible, with the upper half only addressable by register indirect addressing). a small rom of 512 bytes contains a bootstrap loader that is executed automatically after power on reset or if initiated by software later. the user program is normally loaded into a 4k byte ram 1 from an external serial eeprom by the bootstrap loader. the 4k byte ram may also (partially) be used for data storage in some applications. 1.1.2 boot eeprom/flash the program code for the device must be loaded from an external non-volatile memory. the default boot loader expects this to be a ?generic 25320? eeprom with spi interface. these memories are available from several vendors with supply ranges down to 1.8v. the spi interface uses the pins miso (from eeprom sdo), sck (to eeprom sck), mosi (to eeprom sdi) and eecsn (to eeprom csn). when the boot is completed, the miso (p1.2), mosi (p1.0) and sck (p1.1) pins may be used for other purposes such as other spi devices or gpio (general purpose input output). 1.1.3 register map the sfr (special function registers) control several of the features of the nrf9e5. most of the nrf9e5 sfrs are identical to the standard 8051 sfrs. however, there are additional sfrs that control features that are not available in the standard 8051. the sfr map is shown in table 3 . the registers with grey background are registers with industry standard 8051 behavior. note that the function of p0, p1 and p2 are somewhat different from the ?standard? even if the conventional addresses (0x80, 0x90 and 0xa0) are used. 1 optionally this 4k block of memory can be configured as 2k mask rom and 2k ram or 4 k mask rom
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 6 of 104 june 2004 x000 x001 x010 x011 x100 x101 x110 x111 f8 eip hwrev f0 b e8 eie e0 acc d8 eicon d0 psw c8 t2con rcap2l rcap2h tl2 th2 c0 b8 ip cklf con b0 rstrea s spi _data spi _ctrl spi clk tick_ dv ck_ ctrl test_ mode a8 ie pwm con pwm duty regx _msb regx _lsb regx _ctrl a0 p2 98 scon sbuf 90 p1 exif mpage p0_drv p0_dir p0_alt p1_dir p1_alt 88 tcon tmod tl0 tl1 th0 th1 ckcon spc_fnc 80 p0 sp dpl0 dph0 dpl1 dph1 dps pcon table 3 sfr register map. 1.2 pwm the nrf9e5 has one programmable pwm (pulse-width modulation) output, which is the alternate function of p0.7. the resolution of the pwm is software programmable to 6, 7 or 8 bits. the frequency of the pwm signal is programmable via a 6 bit prescaler from the xtal oscillator. the duty cycle is programmable between 0% and 100% via one 8-bit register. 1.3 spi nrf9e5 features a simple single buffered spi (serial programmable interface) master. the 3 data lines of the spi bus (miso, sck and mosi) are multiplexed (by writing to register spi_ctrl) between the gpio pins (lower 3 bits of p1) and the rf transceiver and ad subsystems. the spi hardware does not generate any chip select signal. the programmer will typically use gpio bits (from port p0) to act as chip selects for one or more external spi devices. the eecsn pin is a general purpose io dedicated as chip select for the boot eeprom. when the spi interfaces the rf transceiver, the chip selects are available in an internal gpio port, p2. 1.4 port logic the device has 8 general-purpose bi-directional pins (the p0 port). additionally the 4 spi data pins may be used as general purpose io (the p1). most of the gpio pins can be used for multiple purposes under program control. the alternate functions include two external interrupts, uart rxd and txd, a spi master port, three enable/count signals for the timers and the pwm output and a slow programmable timer. each pin in the p0 port can be programmed for high sink or source current.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 7 of 104 june 2004 1.5 power management the nrf9e5 can be placed into several low power modes under program control, and also the adc and rf subsystems can be turned on or off under program control. the cpu will stop, but all ram?s and registers maintain their values. the watchdog, rtc (real time clock) wakeup timer and the gpio wakeup function are always active during power down. the current consumption is typically 2.5a when running with the crystal oscillator off. the device can exit the power down modes by an external pin, an event on any of the p0 gpio pins, by the wakeup timer if enabled or by a watchdog reset. 1.6 lf clock, rtc wakeup timer, gpio wakeup and watchdog the nrf9e5 contains an internal low frequency clock cklf that is always on. when the crystal oscillator clocks the circuit, the cklf is a 4khz clock derived from the crystal oscillator. when no crystal oscillator clock is available, the cklf is a low power rc oscillator that cannot be disabled, so it will run continuously as long as vdd = 1.8v. the rtc wakeup timer, the gpio wakeup and watchdog all run on the cklf to ensure these vital functions will work during all power down modes. rtc wakeup timer is a 24 bit programmable down counter and the watchdog is a 16 bit programmable down counter. the resolution of the watchdog and wakeup timer is programmable (with prescaler tick_dv) from approximately 300s to approximately 80ms. by default the resolution is 1ms. the wakeup timer can be started and stopped by user software. the watchdog is disabled after a reset, but if activated it cannot be disabled again, except by another reset. an rtc wakeup timer timeout also provides a programmable pulse (gtimer) that can be an output on a gpio pin. the gpio wakeup function lets the software enable wakeup on one or more pins from the p0 gpio port. the edge sensitivity (rising, falling or both) and de-bouncing filter is individually programmable for each pin. 1.7 xtal oscillator the microcontroller, ad converter and transceiver run on the same crystal oscillator generated clock. a range of crystals frequencies from 4 to 20 mhz may be utilized. for details, please see chapter 7.1 on page 17 . the oscillator may be started and stopped as requested by software.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 8 of 104 june 2004 1.8 ad converter the nrf9e5 ad converter has up to 10-bit dynamic range and linearity with a conversion rate of 80 ksps used at the nyquist rate. the reference for the ad converter is software selectable between the aref input and an internal 1.22v bandgap reference. the converter has 5 inputs selectable by software. selecting one of the inputs 0 to 3 will convert the voltage on the respective ain0 to ain3 pin. input 4 enables software to monitor the nrf9e5 supply voltage by converting an internal input that is vdd/3 with the 1.22v internal reference selected. the ad converter is typically used in a start/stop mode. the sampling time is then under software control. the converter is by default configured as 10 bits. for special requirements, the ad converter can be configured by software to perform 6, 8 or 12 bit conversions. the converter may also be used in differential mode with ain0 used as negative input and one of the other 3 external inputs used as noninverting input. 1.9 radio transceiver the transceiver part of the circuit has identical functionality to the nrf905 single chip rf transceiver. it is accessed through an internal parallel port and / or an internal spi. the data ready, carrier-detect and address match signals can be programmed as interrupts to the microcontroller or polled via a gpio port. the nrf905 is a radio transceiver for the 433/868/915 mhz ism bands. the transceiver consists of a fully integrated frequency synthesizer, a power amplifier, a modulator and a receiver unit. output power and frequency channels and other rf parameters are easily programmable by use of the on chip spi interface to the nrf905 core. rf current consumption is only 11 ma in tx mode (output power -10dbm) and 12.5 ma in rx mode. for power saving the transceiver can be turned on / off under software control. this document should be read in conjunction with the nrf905 datasheet.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 9 of 104 june 2004 2 eletrical specification symbol parameter (condition) notes min. typ. max. units operating conditions vdd supply voltage 1.9 3.0 3.6 v temp operating temperature -40 27 85 oc digital input pin v ih high level input voltage vdd-0.3 vdd v v il low level input voltage vss 0.3 v digital output pin v oh high level output voltage (i oh =-0.5ma) vdd-0.3 vdd v v ol low level output voltage (i ol =0.5ma) vss 0.3 v general electrical specification i pd supply current in power down mode 2.5 m a general microcontroller conditions i vdd_mcu supply current @4mhz @3v 1 ma i ol_hd high drive sink current for p06, p04, p02 and p00 @ vol = 0.4v 1) 10 ma i oh_hd high drive source current for p07, p05, p03 and p01 @ voh = vdd-0.4v 1) 10 ma f lp_osc low power rc oscillator frequency 1 5.5 khz general rf conditions f op operating frequency 2) 430 928 mhz f xtal crystal frequency 3) 4 20 mhz d f frequency deviation 42 50 58 khz r gfsk gfsk data rate, manchester-encoded 100 kbps f ch_433 channel spacing @ 433mhz 100 khz f ch_868 channel spacing @ 868 and 915 mhz 200 khz transmitter operation p rf10 output power 10dbm setting 4) 7 10 11 dbm p rf6 output power 6dbm setting 4) 3 6 9 dbm p rf-2 output power ?2dbm setting 4) -6 -2 2 dbm p rf-10 output power -10dbm setting 4) -14 -10 -6 dbm p bw 20db bandwidth for modulated carrier 190 khz p rf1 1 st adjacent channel transmit power 5) -27 dbc p rf2 2 nd adjacent channel transmit power 5) -54 dbc i tx10dbm supply current @ 10dbm output power 30 ma i tx-14dbm supply current @ -10dbm output power 11 ma receiver operation i rx supply current in receive mode 12.5 ma rx sens sensitivity at 0.1%ber -100 dbm rx max maximum received signal 0 dbm c/i co c/i co-channel 6) 13 db c/i 1s t 1 st adjacent channel selectivity c/i 200khz 6) -7 db c/i 2nd 2 nd adjacent channel selectivity c/i 400khz 6) -16 db c/i im image rejection 6) -30 db table 4 nrf9e5 electrical specification.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 10 of 104 june 2004 symbol parameter (condition) notes min. typ. max. units adc operation dnl differential nonlinearity f in = 0.9991 khz 0.5 lsb inl integral nonlinearity f in = 0.9991 khz 0.75 lsb snr signal to noise ratio (dc input) 59 dbfs v os midscale offset 1 %fs e g gain error 1 %fs snr signal to noise ratio (without harmonics) f in = 10 khz 53 58 dbfs sfdr spurious free dynamic range f in = 10 khz 65 db v bg internal reference 1.1 1.22 1.3 v internal reference voltage drift 100 ppm/ c v fs reference voltage input (external ref) 0.8 1.5 v f s conversion rate 7) 125 ksps i adc supply current adc operation 1 ma t npd start-up time from adc power down 15 m s table 5 nrf9e5 ad converter electrical specifications. 1) higher sink/source current is possible if increased voltage changes on ports are accepted. 2) operates in the 433, 868 and 915 mhz ism band. 3) the crystal frequency may be chosen from 5 different values (4, 8, 12, 16, and 20mhz) which are specified in the configuration word. please see table 22 on page 37 . 4) optimum load impedance. 5) channel width and channel spacing is 200khz. 6) channel level +3db over sensitivity, interfering signal a standard carrier wave, image 2 mhz above wanted. 7) conversion rate is dependant on resolution, please see chapter 10.3 page 31 . 2.1 detailed current information mode typical current light power down 0.4 ma moderate power down 125 ua standby mode 25 ua deep power down 2.5 ua mcu @0.5m 3 volt 0.125 ma mcu @1m 3 volt 0.25 ma mcu @2m 3 volt 0.5 ma mcu @4m 3 volt 1 ma mcu @8m 3 volt 2 ma mcu @12m 3 volt 3 ma mcu @16m 3 volt 4 ma mcu @20m 3 volt 5 ma rx @ 433 12.2 ma rx @ 868/915 12.8 ma reduced rx 10.5 ma tx @ 10dbm 30 ma tx @ 6dbm 20 ma tx @ -2dbm 14 ma tx @ -10dbm 11 ma table 6 detailed current information
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 11 of 104 june 2004 3 pin assignment nrf9e5 32l qfn 5x5 miso vss p04 dvdd_1v2 p05 xc2 vss p06 p07 ant2 vdd_pa vss ant1 vss ain0 vdd vss p01 xc1 4 3 2 1 6 5 7 8 9 13 14 12 15 10 11 16 24 23 22 20 19 21 18 17 29 28 27 30 26 25 31 32 vdd aref p00 iref ain1 ain2 ain3 mosi p02 p03 vdd eecsn sck figure 2 pin assignment nrf9e5.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 12 of 104 june 2004 4 pin function pin name pin function description 1 p01 digital in/out up bi-directional digital pin 2 p02 digital in/out up bi-directional digital pin 3 p03 digital in/out up bi-directional digital pin 4 vdd power power supply (+3v dc) 5 vss power ground (0v) 6 p04 digital in/out up bi-directional digital pin 7 p05 digital in/out up bi-directional digital pin 8 p06 digital in/out up bi-directional digital pin 9 p07 digital in/out up bi-directional digital pin 10 mosi spi-interface spi output 11 miso spi-interface spi input 12 sck spi-clock spi clock 13 eecsn spi-enable spi enable, active low 14 xc1 analog input crystal pin 1/ external clock reference pin 15 xc2 analog output crystal pin 2 16 vss power ground (0v) 17 vdd power power supply (+3v dc) 18 vss power ground (0v) 19 vdd_pa power output regulated positive supply (1.8v) to nrf905 power amplifier 20 ant1 rf ? port antenna interface 1 21 ant2 rf ? port antenna interface 2 22 vss power ground (0v) 23 iref analog input reference current 24 vss power ground (0v) 25 vdd power power supply (+3v dc) 26 ain3 analog input adc input 3 27 ain2 analog input adc input 2 28 ain1 analog input adc input 1 29 ain0 analog input adc input 0 30 aref analog input adc reference voltage 31 dvdd_1v2 power output low voltage positive digital supply output for de-coupling 32 p00 digital in/out up bi-directional digital pin table 7 nrf9e5 pin function.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 13 of 104 june 2004 5 system clock the microcontroller clock, cpu_clk, is generated from the on chip crystal oscillator. cpu_clk frequency is configured in the rf-configuration register (see chapter 11 ) and could be set to 0.5, 1, 2 or 4mhz. cpu_clk could in addition be set equal to the crystal oscillator frequency itself. the cpu_clk generation is illustrated in figure 3 . it is important to always set xof equal to the actual crystal selected for the application. xo f xo divide 1 to 5 divide 1 to 4 4mhz up_clk_freq 0.5 - 4mhz mux f cpu_clk 0.5 to 20mhz xof up_clk _freq up_clk_en figure 3 cpu_clk generation in nrf9e5. the chip has an internal low frequency clock that is always active. this clock ensure proper operation of vital function when the chip is in power down mode and the crystal oscillator is turned off, please see chapter 16 on page 51 .
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 14 of 104 june 2004 6 digital i/o ports the nrf9e5 has two io ports located at the default locations for p0 and p1 in standard 8051, but the ports are fully bi-directional cmos and the direction of each pin is controlled by a _dir and an _alt bit for each bit as shown in the table below. pin default function alternate=1 spi_ctrl != 01 eecsn p1.3 p1.3 miso spi.datain p1.2 sck spi.clock t2 (timer2 input) p1.0 mosi spi.dataout p1.1 p00 p0.0 gtimer p01 p0.1 rxd (uart) p02 p0.2 txd (uart) p03 p0.3 int0_n (interrupt) p04 p0.4 int1_n (interrupt) p05 p0.5 t0 (timer0 input) p06 p0.6 t1 (timer1 input) p07 p0.7 pwm table 8 port functions. 6.1 i/o port behavior during reset during this period the internal reset is active (regardless of whether or not the clock is running), all the port pins related to p0 are configured as inputs, whereas the inputs related to p1 are configured as required for an spi master. when program execution starts, all ports are still configured as during reset, and the program will need to set the _alt and/or the _dir register for the pins that need another direction. 6.2 port 0 (p0) p0_alt and p0_dir control the p0 port function in that order of priority. if the alternate function for port p0.n is set (by p0_alt.n = 1) the pin will be input or output as required by the alternate function (uart, external interrupt, timer inputs or pwm output), except that the uart rxd direction will still depend on p0_dir.1. to use int0_n or int1_n as interrupts, the corresponding alternate function must be activated, p0_alt.3 / p0_alt.4. when the p0_alt.n is not set, bit ?n? of the port is a gpio function with the direction controlled by p0_dir.n. data in p0_alt.n,p0_dir.n pin 10 11 00 01 p00 gtimer out gtimer out p0.0 out p0.0 in p01 rxd out rxd in p0.1 out p0.1 in p02 txd out txd out p0.2 out p0.2 in p03 int0_n in int0_n in p0.3 out p0.3 in p04 int1_n in int1_n in p0.4 out p0.4 in p05 t0 in t0 in p0.5 out p0.5 in p06 t1 in t1 in p0.6 out p0.6 in p07 pwm out pwm out p0.7 out p0.7 in table 9 port 0 (p0) functions.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 15 of 104 june 2004 port 0 is controlled by sfr-registers 0x80, 0x93, 0x94 and 0x95 listed in the table below. addr sfr (hex) r/w #bit init value (hex) name function 80 r/w 8 ff p0 port 0, pins p07 to p00 93 r/w 8 00 p0_drv high drive strength for each bit of port 0 0: enable, 1: disable (see 6.2.1 below for a description) 94 r/w 8 ff p0_dir direction for each bit of port 0 0: output, 1: input direction is overridden if alternate function is selected for a pin. 95 r/w 8 00 p0_alt select alternate functions for each pin of p0, if corresponding bit in p0_alt is set, as listed in table 9 port 0 (p0) functions . table 10 port 0 control and data sfr-registers. 6.2.1 high current drive capability odd numbered bits will source high current when the corresponding bit in p0_drv is set, where as even number bits will sink high current when the corresponding bit in p0_drv is set. 6.3 port 1 (p1 or spi port) the p1 port consists of 4 pins, one of which is a hardwired input. the primary function of the p1 port (when spi_ctrl is 01) is a spi master port. the pin eecsn is used as a chip select for the boot eeprom, the gpio bits in port p0 may be used as chip select(s) for other spi devices. when not used as spi port, p1_alt.0 will force sck (p1.0) to be the timer t2 input; mosi (p1.1) is now a gpio. when p0_alt.0 is 0, also sck (p1.0) is a gpio. miso (p1.2) is always an input. that is p1_dir.2 and p1_alt.2 are ignored. eecsn (p1.3) is always a gpio. it will be activated by the default boot loader after reset and should be connected to the csn of the boot flash. spi_ctrl != 01 p1_alt.n = 0 pin spi_ctrl = 01 p1_alt.n = 1 p1_dir.n = 0 p1_dir.n = 1 sck spi.clock out t2 in p1.0 in p1.0 out mosi spi.dataout out p1.1 i/o 2 p1.1 in p1.1 out miso spi.datain in p1.2 in p1.2 in p1.2 in eecsn p1.3 out p1.3 i/o 2 p1.3 in p1.3 out table 11 port 1 (p1) functions. 2 p1.1 and p1.3 are actually under control of p1_dir.1 and p1_dir.3 even when p1_alt.1 or p1_alt.3 are 1, since there are no alternate functions for these pins.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 16 of 104 june 2004 port 1 is controlled by sfr-registers 0x90, 0x96 and 0x97, and only the 4 lower bits of the registers are used. addr sfr (hex) r/w #bit init value (hex) name function 90 r/w 4 f p1 port 1, pins spi_sck, spi_mosi, spi_miso and spi_csn 96 r/w 4 4 p1_dir direction for each bit of port 1 0: output, 1: input direction is overridden if alternate function is selected for a pin, or if spi_ctrl=01. spi_miso is always input. 97 r/w 4 0 p1_alt select alternate functions for each pin of p1 if corresponding bit in p1_alt is set, as listed in table 11 port 1 (p1) functions table 12 port 1 control and data sfr-registers. p1 is by default configured as a spi master port. in this case, it is then controlled by the 3 sfr registers 0xb2, 0xb3 and 0xb4 as shown in table 33 on page 43 .
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 17 of 104 june 2004 7 analog interface 7.1 crystal specification tolerance includes initially accuracy and tolerance over temperature and aging. frequency c l esr c 0max tolerance @ 868/915 mhz tolerance @ 433 mhz 4mhz 12pf 150 w 7.0pf 30ppm 60ppm 8mhz 12pf 100 w 7.0pf 30ppm 60ppm 12mhz 12pf 100 w 7.0pf 30ppm 60ppm 16mhz 12pf 100 w 7.0pf 30ppm 60ppm 20mhz 12pf 100 w 7.0pf 30ppm 60ppm table 13 crystal specification of nrf9e5 . to achieve a crystal oscillator solution with low power consumption and fast start-up time, it is recommended to specify the crystal with a low value of crystal load capacitance. specifying c l =12pf is acceptable, but it is possible to use up to 16pf. specifying a lower value of crystal parallel equivalent capacitance, co=1.5pf is also good, but this can increase the price of the crystal itself. typically co=1.5pf at a crystal specified for co_max=7.0pf. 7.2 antenna output the ?ant1 & ant2? output pins provide a balanced rf output to the antenna. the pins must have a dc path to vdd_pa, either via a rf choke or via the center point in a dipole antenna. the load impedance seen between the ant1/ant2 outputs should be in the range 200-700 w . the optimum differential load impedance at the antenna ports is given as: 900mhz 225 w +j210 430mhz 300 w +j100 a low load impedance (for instance 50 w ) can be obtained by fitting a simple matching network or a rf transformer (balun). further information regarding balun structures and matching networks may be found in the application examples chapter. 7.3 adc inputs the analog to digital converter has four analog input channels and one reference voltage input. analog input is selected with chsel in the adc_config_reg. 7.4 current reference to get accurate internal biasing, an external low tolerance resistor is used. a resistor of 22k w and 1% accuracy should be connected between the pin iref and ground for proper operation of nrf9e5 .
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 18 of 104 june 2004 7.5 digital power de-coupling nrf9e5 has internal regulator used for optimum performance and minimum power dissipation in digital part of the system. de-coupling of the regulated power is needed for proper operation of the chip. a capacitor of 10nf should be connected between dvdd_1v2 and ground as close to the chip as possible. please see pcb layout and de- coupling guidelines for further information regarding layout.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 19 of 104 june 2004 8 internal interface ad converter and transceiver 8.1 p2 - radio general purpose io port the p2 port controls the transceiver. the p2 port uses the address normally used by port p2 in standard 8051. however since the radio transceiver is on chip, the port is not bi- directional. the power on default values in the port ?latch? also differs from traditional 8051 to match the requirements of the radio transceiver subsystem. operation of the transceiver is controlled by sfr registers p2 and spi_ctrl: addr sfr (hex) r/w #bit init value (hex) name function a0 r/w 8 04 p2 general purpose io for interface to nrf905 radio transceiver and ad converter subsystems b3 r/w 2 0 spi_ctrl 00 -> spi not used 01 -> spi connected to port p1 (boot) 1x -> spi connected to nrf905/ad table 14 nrf905 433/868/915 mhz transceiver subsystem control registers - sfr 0xa0 and 0xb3. the bits of the p2 register correspond to similar pins of the nrf905 single chip, as shown in table 15 p2 (radio) register . in the documentation the pin names are used, so please note that setting or reading any of these nrf905 pins, means to write or read the p2 sfr register accordingly. p2 register bit: function corresponding nrf905 transceiver pin name read : 7: nrf905 transceiver address match am 6: nrf905 transceiver carrier detect cd 5: nrf905 transceiver data ready dr 4: adc end of conversion eoc 3: 0 (not used) 2: nrf905 transceiver and adc spi data out (sbmiso) miso 1: 0 (not used) 0: 0 (not used) write : 7: not used 6: not used 5: nrf905 transceiver enable receiver function trx_ce 4: nrf905 transceiver transmit/receive selection tx_en 3: nrf905 transceiver and adc spi chip select (racsn) csn 2: not used 1: nrf905 transceiver and adc spi data in (sbmosi) mosi 0: nrf905 transceiver and adc spi clock (sbsck) sck table 15 p2 (radio) register - sfr 0xa0, default initial data value is 0x08. note : some of the pins are overridden when spi_ctrl=1x, see table 14 .
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 20 of 104 june 2004 8.1.1 controlling the transceiver via spi interface. normally the spi hardware interface rather than gpio programming will do the data transfers to the transceiver. please see table 33 spi control and data sfr-registers for use of spi interface. when spi_ctrl is ?0x?, all radio pins are connected directly to their respective port pins and the spi functionality may be implemented in software. 7 6 5 4 3 2 1 0 eoc am dr cd sbmiso trx_ce tx_en sbcsn sbmosi sbsck p2 register bit read write spi hardware eoc am dr cd csn mosi sck miso trx_ce tx_en mux mux dataout clock mux nrf905/ad from io-pin 1 0 1 0 0 1 datain spi_ctrl==1x figure 4 transceiver interface. 8.1.2 p2 port behavior during reset during the period the internal reset is active (regardless of whether or not the clock is running), the p2 outputs that control the nrf905 transceiver subsystem are forced to their respective default values. when program execution starts, these ports will remain at those default levels until the programmer actively changes them by writing to the p2 register.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 21 of 104 june 2004 9 tranceiver subsystem ( n rf905) 9.1 rf modes of operation the transceiver has two active (rx/tx) modes and one power-saving mode when the microcontroller is running. 9.1.1 active mo des shockburst? rx shockburst? tx 9.1.2 power saving mode standby and spi - programming the transceiver mode is decided by the settings of trx_ce, tx_en trx_ce tx_en operating mode 0 x standby and spi ? programming 1 0 radio enabled - shockburst tm rx 1 1 radio enabled - shockburst tm tx table 16 transceiver operational modes. 9.2 nrf shockburst? mode the nrf9e5 uses the nordic semiconductor shockburst? feature. shockburst tm makes it possible to use the high data rate offered by the nrf905. by embedding all high speed signal processing related to rf protocol in the transceiver, the nrf905 offers the micro controller a simple spi interface. data rate is decided by the interface-speed the micro controller itself sets up. by allowing the digital part of the application to run at low speed, while maximizing the data rate on the rf link, the nrf905 shockburst? mode reduces the average current consumption in applications. in shockburst tm rx, address match (am) and data ready (dr) notifies the mcu when a valid address and payload is received respectively. in shockburst tm tx, the nrf905 automatically generates preamble and crc. data ready (dr) notifies the mcu that the transmission is completed. all together, this means reduced memory demand and more available resources in the mcu, as well as reduced software development time.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 22 of 104 june 2004 typical shockburst tm tx: 1. when the application mcu has data for a remote node, the address of the receiving node (tx-address) and payload data (tx-payload) are clocked into nrf905 via the spi interface. the application protocol or mcu sets the speed of the interface. 2. mcu sets trx_ce and tx_en high, this activates a nrf905 shockburst? transmission. 3. nrf905 shockburst?: radio is automatically powered up. data package is completed (preamble added, crc calculated). data package is transmitted (100kbps, gfsk, manchester-encoded). data ready is set high when transmission is completed. 4. if auto_retran is set high, the nrf905 continuously retransmits the package until trx_ce is set low. 5. when trx_ce is set low, the nrf905 finishes transmitting the outgoing package and then sets itself into standby mode. the shockburst tm mode ensures that a transmitted package that has started always finishes regardless of what trx_en and tx_en is set to during transmission. the new mode is activated when the transmission is completed. please see subsequent chapters for detailed timing for test purposes such as antenna tuning and measuring output power it is possible to set the transmitter so that a constant carrier is produced. to do this trx_ce must be maintained high instead of being pulsed. in addition auto retransmit should be switched off. after the burst of data has been sent then the device will continue to send the unmodulated carrier.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 23 of 104 june 2004 spi - programming ucontroller loading addr and payload data (configuration register if changes since last tx/rx) no yes nrf shockburst tx generate crc and preamble sending package dr is set high when completed transmitter is powered up trx_ce = hi ? auto_ retran = hi ? yes no yes no addr payload data package bit in configuration register trx_ce = hi ? radio in standby tx_en = hi pwr_up = hi trx_ce = lo addr payload crc pre- amble dr is set low after pre- amble nb: dr is set low under the following conditions after it has been set high: if tx_en is set low figure 5 flowchart shockburst tm transmit of nrf905.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 24 of 104 june 2004 typical shockburst tm rx: 1. shockburst tm rx is selected by setting trx_ce high and tx_en low. 2. after 650 m s nrf905 is monitoring the air for incoming communication. 3. when the nrf905 senses a carrier at the receiving frequency, carrier detect (cd) pin is set high. 4. when a valid address is received, address match (am) pin is set high. 5. when a valid package has been received (correct crc found), nrf905 removes the preamble, address and crc bits, and the data ready (dr) pin is set high. 6. mcu sets the trx_ce low to enter standby mode (low current mode). 7. mcu can clock out the payload data at a suitable rate via the spi interface. 8. when all payload data is retrieved, nrf905 sets data ready (dr) and address match (am) low again. 9. the chip is now ready for entering shockburst tm rx, shockburst t m tx or power down mode. if trx_ce or tx_en is changed during an incoming package, the nrf905 changes mode immediately and the package is lost. however, if the mcu is sensing the address match (am) pin, it knows when the chip is receiving an incoming package and can therefore decide whether to wait for the data ready (dr) signal or enter a different mode. to avoid spurious address matches it is recommended that the address length be 24 bits or higher in length. small addresses such as 8 or 16 bits can often lead to statistical failures due to the address being repeated as part of the data packet. this can be avoided by using a longer address. each byte within the address should be unique. repeating bytes within the address reduces the effectiveness of the address and increases its susceptibility to noise hence increasing the packet error rate. the address should also have several level shifts (i.e. 10101100) to reduce the statistical effect of noise and hence reduce the packet error rate.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 25 of 104 june 2004 figure 6 flowchart shockburst tm receive of nrf905. no yes receiver is powered up no yes receiving data receiver sensing for incomming data cd is set high if carrier am is set high no dr high is set high radio enters stby mcu clocks out payload via the spi interface dr and am are set low yes yes no am is set low radio in standby tx_en = lo pwr_up = hi trx_ce = hi ? correct addr? correct crc? trx_ce = hi ? payload data package addr payload crc pre- amble rx remains on mcu clocks out payload via the spi interface dr and am are set low
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 26 of 104 june 2004 9.3 standby mode standby mode is used to minimize average current consumption while not transmitting or receiving and still maintaining short start up times to shockburst tm rx and shockburst tm tx. in this mode the crystal oscillator have to be active. the configuration word content is maintained during standby. 9.4 output power adjustment the power amplifier in nrf905 can be programmed to four different output power settings by the configuration register. by reducing output power, the total tx current is reduced. power setting rf output power dc current consumption 00 -10 dbm 11.0 ma 01 -2 dbm 14.0 ma 10 6 dbm 20.0 ma 11 10 dbm 30.0 ma conditions: vdd = 3.0v, vss = 0v, ta = 27oc, load impedance = 400 w . table 17 rf output power setting for the nrf905 . 9.5 modulation the modulation of nrf905 is gaussian frequency shift keying (gfsk) with a data-rate of 100kbps. deviation is 50khz. gfsk modulation results in a more bandwidth effective transmission-link compared with ordinary fsk modulation. the data is internally manchester encoded (tx) and manchester decoded (rx). that is, the effective symbol-rate of the link is 50kbps. by using internally manchester encoding, no scrambling in the u-controller is needed.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 27 of 104 june 2004 9.6 output frequency the operating rf-frequency of nrf905 is set in the configuration register by ch_no and hfreq_pll. the operating frequency is given by: mhz pll hfreq no ch f op ) _ 1 ( )) 10 / _ ( 4 . 422 ( + + = when hfreq_pll is ?0? the frequency resolution is 100khz and when it is ?1? the resolution is 200khz. the application operating frequency has to be chosen to apply with the short range devise regulation in the area of operation. operating frequency hfreq_pll ch_no 430.0 mhz [0] [001001100] 433.1 mhz [0] [001101011] 433.2 mhz [0] [001101100] 434.7 mhz [0] [001111011] 862.0 mhz [1] [001010110] 868.2 mhz [1] [001110101] 868.4 mhz [1] [001110110] 869.8 mhz [1] [001111101] 902.2 mhz [1] [100011111] 902.4 mhz [1] [100100000] 927.8 mhz [1] [110011111] table 18 examples of real operating frequencies. 9.7 carrier detect. when the nrf905 is in shockburst tm rx, the carrier detect (cd) pin is set high if a rf carrier is present at the channel the device is programmed to. this feature is very effective to avoid collision of packages from different transmitters operating at the same frequency. whenever a device is ready to transmit it could first be set into receive mode and sense whether or not the wanted channel is available for outgoing data. this forms a very simple listen before transmit protocol. operating carrier detect (cd) with reduced rx power mode is an extremely power efficient rf system. typical carrier detect level (cd) is typically 5db lower than sensitivity, i.e. if sensitivity is ?100dbm then the carrier detect function will sense a carrier wave as low as ?105dbm. below ?105dbm the carrier detect signal will be low, i.e. 0v. above ?95dbm the carrier detect signal will be high, i.e. vdd. between approximately -95 to -105 the carrier detect signal will toggle.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 28 of 104 june 2004 9.8 address match when the nrf905 is in shockburst tm rx mode, the address match (am) pin is set high as soon as an incoming package with an address that is identical with the device?s own identity is received. with the address match pin the controller is alerted that the nrf905 is receiving data actually before the data ready (dr) signal is set high. if the data ready (dr) pin is not set high i.e. the crc is incorrect then the address match (am) pin is reset to low at the end of the received data packet. this function can be very useful for an mcu. if address match (am) is high then the mcu can make a decision to wait and see if data ready (dr) will be set high indicating a valid data package has been received or ignore that a possible package is being received and switch modes. 9.9 data ready the data ready (dr) signal makes it possible to largely reduce the complexity of the mcu software program. in shockburst tm tx, the data ready (dr) signal is set high when a complete package is transmitted, telling the mcu that the nrf905 is ready for new actions. it is reset to low at the start of a new package transmission or when switched to a different mode i.e. receive mode or standby mode. in shockburst tm tx auto retransmit the data ready (dr) signal is set high at the beginning of the pre-amble and is set low at the end of the preamble. the data ready (dr) signal therefore pulses at the beginning of each transmitted data packet. in shockburst tm rx, the signal is set high when nrf905 has received a valid package, i.e. a valid address, package length and correct crc. the mcu can then retrieve the payload via the spi interface. the data ready (dr) pin is reset to low once the data has been clocked out of the data buffer or the device is switched to transmit mode. 9.10 auto retransmit one way to increase system reliability in a noisy environment or in a system without collision control is to transmit a package several times. this is easily accomplished with the auto retransmit feature in nrf905 . by setting the auto_retran bit to ?1? in the configuration register, the circuit keeps sending the same data package as long as trx_ce and tx_en is high. as soon as trx_ce is set low the device will finish sending the packet it is currently transmitting and then return to standby mode. 9.11 rx reduced power mode to maximize battery lifetime in application where the nrf905 high sensitivity is not necessary; nrf905 offers a built in reduced power mode. in this mode, the receive current consumption reduces from 12.5ma to only 10.5ma. the sensitivity is reduced to typical ?85dbm, 10db. some degradation of the nrf905 blocking performance should be expected in this mode. the reduced power mode is an excellent option when using carrier detect to sense if the wanted channel is available for outgoing data.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 29 of 104 june 2004 10 ad converter subsystem 10.1 ad converter the nrfe5 ad converter has 10 bit dynamic range and linearity when used at the nyquist rate. with lower signal frequencies and post filtering, up to 12 bits resolution is possible. the reference for the ad converter is selectable between the aref input and an internal 1.22v bandgap reference. the converter default spi setting is 10 bits. for special requirements, the ad converter can be configured to perform 6, 8, 10 or 12 bit conversions. the converter may also be used in differential mode with ain0 used as inverting input and one of the other 3 external inputs used as noninverting input. two registers interface the ad converter, adc_config_reg and adc_data_reg. ad converter status bit are available in the status_register. registers are described in detail in chapter 11 . selection of input channel is directly embedded in the start_adc_conv command, alternatively it is set by chsel in the adc_config_reg. values of chsel from 0 to 3 would select ain0 to ain3 respectively. setting chsel to [1xxx] will monitor the nrf9e5 supply voltage by converting an internal input that is vdd/3 with the 1.22v internal reference. the ad conversion result is available as adcdata in adc_data_reg at the end of conversion. the data in adc_data_reg is stored according to table 19 with left or right justified data selected by adc_rl_just. adc_data_reg[15:0] adc_ rl_just adc _resctrl # bit high byte [15:8] low byte [7:0] 0 00 6 adcdata[5:0] 0 01 8 adcdata[7:0] ?0? 0 10 10 adcdata[9:0] 0 11 12 adcdata[11:0] 1 00 6 adcdata[5:0] 1 01 8 ?0? adcdata[7:0] 1 10 10 adcdata[9:0] 1 11 12 adcdata[11:0] table 19 adc_data_register justified data. overflow status is stored as adc_rflag in the status_register after each conversion. the complete subsystem is switched off by clearing bit adc_pwr_up. instructions for the ad converter are given in table 21 on page 35 .
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 30 of 104 june 2004 10.2 ad converter usage 10.2.1 measurements with external reference when vfssel is set to 1 and chsel selects an input aini (i.e. ain0 to ain3), the result in adcdata is directly proportional to the ratio between the voltage on the selected input, and the voltage on pin aref: n aref aini adcdata v v 2 = and for differential measurements a similar equation apply: n n aref ain aini adcdata v v v 2 2 ) 1 ( 0 - - = - where n is the number of bits set in resctrl this mode of operation is normally selected for sources where the voltage is depending on the supply voltage (or another variable voltage), as shown in figure 7 below. the resistor r1 is selected to keep aref = 1.5v for the maximum vdd voltage. r2 r3 r1 aref ain0 ain1 vdd nrf9e5 supply figure 7 typical use of ad with 2 ratiometric inputs.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 31 of 104 june 2004 10.2.2 measurements with internal reference when vfssel is set to 0 and chsel selects an input aini (i.e. ain0 to ain3), the result in adcdata is directly proportional to the ratio between the voltage on the selected input and the internal bandgap reference (nominally 1.22v): n aini adcdata v 2 22 . 1 = and for differential measurements a similar equation apply: n n ain aini adcdata v v 2 2 22 . 1 ) 1 ( 0 - - = - where n is the number of bits set in resctrl this mode of operation is normally selected for sources where the voltage is not depending on the supply voltage. 10.2.3 supply voltage measurement when chsel is set to [1xxx], the adc will use the internal bandgap reference (nominally 1.22v). the input to the converter is 1/3 of the voltage on the vdd pins. the result in adcdata is thus directly proportional to the vdd voltage. n vdd adcdata v 2 66 . 3 = where n is the number of bits set in resctrl 10.3 ad converter sampling and timing an ad conversion is initialized after a low to high transition on cstasrt in adc_config_reg or by using the instruction start_adc_conv. in both cases the conversion itself would start at the first positive edge of adcclk after racsn is set high after instruction is issued. when adcrun is low, a single conversion would be performed and a pulse on eoc is generated when the converted value is available in adc_data_reg. if cstartn is set low or a new start_adc_conv command is issued, the previous conversion will be aborted. conversion time, t conv , depends on resolution. cycles adcclk n t conv 3 2 + = where n is the number of resolution bit. in figure 8 a 10-bit conversion is shown.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 32 of 104 june 2004 adcclk sbcsn eoc adcdata t conv analog sampled figure 8 timing diagram single step conversion. when adcrun is high the adc is running continuously. cycle time t cycle is the time between each conversion. eoc indicates every time a new conversion value is stored in adc_data_reg. cycles adcclk n t cycle 1 2 + = where n is number of resolution bits. figure 9 shows 10-bit conversion where adcrun is set high. adcclk eoc adcdata t conv analog sample t cycle n sample n-1 sample n n+1 n+2 figure 9 timing diagram continuous mode conversion. a 500 khz clock (adcclk) clocks the adc converter. table 20 shows t cycles as function of resolution. resolution [number of bits] t cycles [ m s] sampling rate [kspls] 6 8 125 8 10 100 10 12 83.3 12 14 71.4 table 20 adc resolution and maximum sampling rate.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 33 of 104 june 2004 11 tranceiver and ad converter configuration all configuration of the transceiver and ad converter subsystem is done via an internal spi -interface of the two systems. the interface consists of 7 registers, a spi instructions set is used to decide which operation shall be performed. the spi-interface can only be activated when the transceiver is in standby mode. all references to the spi interface in this chapter refer to the internal spi interface of the transceiver and ad converter subsystem. 11.1 internal spi register configuration the spi-interface consists of seven internal registers. a register read-back mode is implemented to allow verification of the register contents tx-payload en dta clk i/o-reg csn mosi miso sck rf-configuration- register en dta clk tx-address en dta clk status-register en clk adc-configuration- register en dta clk rx-payload en clk adc-data- register en dta clk figure 10 spi ? interface composed of seven internal registers. status ? register register contains status of data ready (dr), address match (am), adc_end_of_conversion and adc_ready_flag adc- configuration ? register register contains information of adc setup such as resolution control, channel select, differential or single ended mode, continuous or single conversion mode etc.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 34 of 104 june 2004 adc- data ? register register contains ad converter results. rf - configuration register register contains transceiver setup information such as frequency and output power ext. tx ? address register contains address of target device. how many bytes used is set in the configuration register. tx ? payload register containing the payload information to be sent in a shockburst tm package. how many bytes used is set in the configuration register. rx ? payload register containing the payload information derived from a received valid shockburst tm package. how many bytes used is set in the configuration register. valid data in the rx-payload register is indicated with a high date ready (dr) signal.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 35 of 104 june 2004 11.2 spi ? instruction set the available commands to be used on the spi-interface are given in table 21 . whenever csn is set low the interface would expect an instruction. every new instruction has to be presided by a high to low transaction on csn. instruction set for the transceiver and ad converter subsystem instruction name instruction format operation w_rf_config (wrc) 0000 aaaa write configuration-register. aaaa indicates which byte the write operation is to be started from. number of bytes depending on start address aaaa. r__rf_config (rrc) 0001 aaaa read configuration-register. aaaa indicates which byte the read operation is to be started from. number of bytes depending on start address aaaa. w_tx_payload (wtp) 0010 0000 write tx-payload: 1 ? 32 bytes. a write operation will always start at byte 0. r_tx_payload (rtp) 0010 0001 read tx-payload: 1 ? 32 bytes. a read operation will always start at byte 0. w_tx_address (wta) 0010 0010 write tx-address: 1 ? 4 bytes. a write operation will always start at byte 0. r_tx_address (rta) 0010 0011 read tx-address: 1 ? 4 bytes. a read operation will always start at byte 0. r_rx_payload (rrp) 0010 0100 read rx-payload: 1 ? 32 bytes. a read operation will always start at byte 0. r_adc_data (rad) 0100 000a read adc data. a indicates which byte the read operation is to be started from. w_adc_config (wac) 0100 0100 write adc configuration register: 1 ? 3 bytes. a write operation will always start at byte 0. r_adc_config (rac) 0100 0110 read adc configuration register: 1 ? 3 bytes. a read operation will always start at byte 0. channel_config (cc) 1000 pphc cccc cccc special command for fast setting of ch_no, hfreq_pll and pa_pwr in the configuration register. ch_no= ccccccccc, hfreq_pll = h pa_pwr = pp start_adc_conv (sav) 1100 ssss special command for start of an adc conversion for a given source ? ssss = chsel. table 21 instruction set for the transceiver ad converter subsystem. a read or a write operation may operate on a single byte or on a set of succeeding bytes from a given start address defined by the instruction. when accessing succeeding bytes one will read or write msb of the byte with the smallest byte number first. the content of the status-register will always be read to miso after a high to low transition on csn.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 36 of 104 june 2004 11.3 spi timing data is clocked into or out of the device on the rising edge of the clock pulse. the clock speed is determined by the mcu and may be from 1hz to 10mhz depending on the mcu. the device must be in one of the power saving modes for the configuration registers to be read or written to. csn sck mosi miso 0 1 2 3 7 8 15 command 8 bits, msb = c7 c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 status byte as output, msb = s7 addressed byte as output, msb = o 7 succeeding bytes to addressed byte as output s 7 s 6 s 5 s 4 s 3 s 2 s 1 s 0 o 7 o 6 o 5 o 4 o 3 o 2 o 1 o 0 figure 11 internal spi read operation. csn sck mosi miso 0 1 2 3 7 8 15 command 8 bits, msb = c7 c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 status byte as output, msb = s7 s 7 s 6 s 5 s 4 s 3 s 2 s 1 s 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 first data byte as input, msb = d7 succeeding data bytes as input figure 12 internal spi write operation. the transceiver and ad converter spi interface is controlled by p2 in the micro controller. that is, sck, mosi, miso and csn are p2.0, p2.1, p2.2 and p2.3 respectively. detailed information of mapping is found in chapter 8 .
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 37 of 104 june 2004 11.4 rf configuration ? register description parameter bitwidth description ch_no 9 sets center frequency together with hfreq_pll (default value = 001101100 b = 108 d ). f rf = ( 422.4 + ch_no d /10)*(1+hfreq_pll d ) mhz hfreq_ pll 1 sets pll in 433 or 868/915 mhz mode (default value = 0). '0' ? chip operating in 433mhz band '1' ? chip operating in 868 or 915 mhz band pa_pwr 2 output power (default value = 00). '00' -10dbm '01' -2dbm '10' +6dbm '11' +10dbm rx_red_ pwr 1 reduces current in rx mode by 1.6ma. sensitivity is reduced (default value = 0). '0' ? normal operation '1' ? reduced power auto_ retran 1 retransmit contents in tx ? register as long trx_ce and txen is high (default value = 0). '0' ? no retransmission '1' ? retransmission of data package rx_afw 3 rx-address width (default value = 100). '001' ? 1 byte rx address field width . '100' ? 4 byte rx address field width tx_afw 3 tx-address width (default value = 100). '001' ? 1 byte tx address field width . '100' ? 4 byte tx address field width rx_pw 6 rx-payload width (default value = 100000). '000001' ? 1 byte rx payload field width '000010' ? 2 byte rx payload field width . '100000' ? 32 byte rx payload field width tx_pw 6 tx-payload width (default value = 100000). '000001' ? 1 byte tx payload field width '000010' ? 2 byte tx payload field width . '100000' ? 32 byte tx payload field width rx_ address 32 rx address identity. used bytes depend on rx_afw (default value = e7e7e7e7 h ). up_clk_ freq 2 cpu clock frequency (default value = 11). '00' ? 4mhz '01' ? 2mhz '10' ? 1mhz '11' ? 500khz up_clk_ en 1 cpu clock enable (default value = 1). '0' ? c pu using up_clk_freq frequency '1' ? cpu using xof frequency xof 3 crystal oscillator frequency. must be set according to external crystal resonant-frequency. '000' ? 4mhz (default value = 100) '001' ? 8mhz '010' ? 12mhz '011' ? 16mhz '100' ? 20mhz crc_en 1 crc ? check enable (default value = 1). '0' ? disable '1' ? enable crc_ mode 1 crc ? mode (default value = 1). '0' ? 8 crc check bit '1' ? 16 crc check bit table 22 rf configuration-register description.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 38 of 104 june 2004 11.5 adc - configuration register description parameter bitwidth description cstartn 1 positive edge of this signal will start one ad conversion when adcrun is inactive. this bit is internally synchronized to the adc clock adcrun 1 adc running continuously when active. cstartn is ignored in this case adc_pwr_ up 1 enable adc vfssel 1 select reference for ad converter 0: use internal band gap reference (nominally 1.22v) 1: use external pin aref for reference (ignored if chsel=[1xxx]). chsel 4 cannel select input 0000: ain0 0001: ain1 0010: ain2 0011: ain3 1xxx: internal vdd/3. resctrl 2 set a/d converter resolution: 00: 6 bit 01: 8 bit 10: 10 bit 11: 12 bit diffmode, 1 enable differential measurements, ain0 must be used as inverting input and one of the other inputs ain1 to ain3, as selected by adcsel, must be used as noninverting input. adc_ rl_just 1 select left or right justified data format: 0: data will be left justified in adc_data_reg 1: data will be right justified in adc_data_reg table 23 adc configuration-register description. 11.6 status-register description parameter bitwidth description am 1 address match, indicate that the receiver has received an address equal to its own identity. detailed description in chapter 9.8 . cd 1 carrier detect, indicates that a carrier is found on the receiving channel. detailed description in chapter 9.7 dr 1 data ready, indicate that the receiver has received a data package with correct address and crc. detailed description in chapter 9.9 . eoc 1 end of conversion, indicates that an ad conversion is completed and that data is placed in adc_data_reg. adc_ rflag 3 overflow indication in adc rflag[2]: underflow (adcdata = 0) rflag[1]: overflow (adcdata = 2 n -1) rflag[0]: over range = rflag[1] or rflag[2] table 24 status-register description.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 39 of 104 june 2004 11.7 rf - register contents rf-config_register (r/w) byte # content bit[7:0], msb = bit[7] init value 0 ch_no[7:0] 0110_1100 1 bit[7:6] not used, auto_retran, rx_red_pwr, pa_pwr[1:0], hfreq_pll, ch_no[8] 0000_0000 2 bit[7] not used, tx_afw[2:0] , bit[3] not used, rx_afw[2:0] 0100_0100 3 bit[7:6] not used, rx_pw[5:0] 0010_0000 4 bit[7:6] not used, tx_pw[5:0] 0010_0000 5 rx_address (device identity) byte 0 e7 6 rx_address (device identity) byte 1 e7 7 rx_address (device identity) byte 2 e7 8 rx_address (device identity) byte 3 e7 9 crc_mode,crc_en, xof[2:0], up_clk_en, up_clk_freq[1:0] 1110_0111 table 25 rf config register contents. tx_payload (r/w) byte # content bit[7:0], msb = bit[7] init value 0 tx_payload[7:0] x 1 tx_payload[15:8] x - - x - - x 30 tx_payload[247:240] x 31 tx_payload[255:248] x table 26 tx payload register contents. tx_address (r/w) byte # content bit[7:0], msb = bit[7] init value 0 tx_address[7:0] e7 1 tx_address[15:8] e7 2 tx_address[23:16] e7 3 tx_address[31:24] e7 table 27 tx address register contents. rx_payload (r) byte # content bit[7:0], msb = bit[7] init value 0 rx_payload[7:0] x 1 rx_payload[15:8] x - x - x 30 rx_payload[247:240] x 31 rx_payload[255:248] x table 28 rx payload register contents.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 40 of 104 june 2004 11.8 adc configuration register contents adc_config_reg (r/w) byte # content bit[7:0], msb = bit[7] init value 0 control: chsel[7:4], vfssel, pwr_up, adcrun, cstartn 0000_0001 1 static: bit[7:4] not used, adc_rl_just, diffmode, resctrl[1:0] 0000_0010 table 29 adc configuration register contents. 11.9 adc data register contents adc_data_reg (r) byte # content bit[7:0], msb = bit[7] init value 0 left or right justified data from adc x 1 left or right justified data from adc x table 30 adc data register contents. 11.10 status register contents status_register (r) byte # content bit[7:0], msb = bit[7] init value 0 am, cd, dr, eoc, adc_rflag[2:0], even parity x table 31 status register contents. the length of all registers is fixed. however, the bytes in tx_payload, rx_payload, tx_address and rx_address used in shockburst tm rx/tx are set in the configuration register. register content is not lost when the device enters one of the power saving modes.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 41 of 104 june 2004 12 tranceiver subsytem timing the following timing must be obeyed during nrf905 operation. 12.1 device switching times nrf905 timing max. stby tx shock burst? 650 m s stby rx shock burst? 650 m s rx shock burst? tx shock burst? 550 1 m s tx shock burst? rx shock burst? 550 1 m s notes to table: 1) rx to tx or tx to rx switching is available without re-programming of the rf configuration register. the same frequency channel is maintained. table 32 switching times for nrf905 . 12.2 shockburst tm tx timing mosi csn pwr_up tx_en trx_ce tx data time t0 = radio enabled t1 = t0+10us minimum trx_ce pulse t2 = t0 + 650us.start of tx data transmission t3 = end of data packet, enter standby mode programming of configuration register and tx data register t0 t1 t2 t3 transmitted data 100kbps manchester encoded figure 13 timing diagram for standby to transmit. after a data packet has finished transmitting the device will automatically enter standby mode and wait for the next pulse of trx_ce. if the auto re-transmit function is enabled the data packet will continue re-sending the same data packet until trx_ce is set low.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 42 of 104 june 2004 12.3 shockburst tm rx timing pwr_up tx_en trx_ce rx data time am dr cd t0 = receiver enabled -listening for data t1 = carrier detect finds a carrier t2 = am - correct address found t3 = dr - data packet with correct address/crc 650us to enter rx mode from trx_ce being set high. t0 t1 t2 t3 650us figure 14 timing diagram for standby to receiving. after the data ready (dr) has been set high a valid data packet is available in the rx data register. this may be clocked out in standby mode. after the data has been clocked out via the spi interface the data ready (dr) and address match (am) signals are reset to low.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 43 of 104 june 2004 13 spi nrf9e5 spi is a simple single buffered master. the 3 data lines of the spi bus (miso, sck and mosi) are multiplexed (by writing to register spi_ctrl) between the gpio pins (lower 3 bits of p1) and the rf transceiver and ad converter subsystems. the spi hardware does not generate any chip select signal. the bootstrap loader uses eecsn (gpio p0.3) as chip select for the boot eeprom. on-chip gpio p2.3 is dedicated as chip select for the rf transceiver and ad converter subsystems. gpio pins from port 0 may be used as chip selects for other external spi slaves. the spi hardware is controlled by sfr?s spi_data (0xb2), spi_ctrl (0xb3) and spiclk (0xb4) as explained in table 33 below . addr sfr (hex) r/w #bit init (hex) name function b2 r/w 8 0 spi_data spi data input/output b3 r/w 2 0 spi_ctrl 00 -> spi not used no clock generated 01 -> spi connected to port p1 (as for booting) (see also table 11 port 1 (p1) functions ) 10 -> spi connected to the nrf905 transceiver (see table 15 p2 (radio) register ) b4 r/w 4 0 spiclk divider factor from cpu clock to spi clock 0000: 1/2 of cpu clock frequency 0001: 1/2 of cpu clock frequency 0010: 1/4 of cpu clock frequency 0011: 1/8 of cpu clock frequency 0100: 1/16 of cpu clock frequency 0101: 1/32 of cpu clock frequency 0110: 1/64 of cpu clock frequency other: 1/64 of cpu clock frequency table 33 spi control and data sfr-registers.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 44 of 104 june 2004 14 pwm the nrf9e5 pwm output is a one-channel pwm with a 2 register interface. the first register, pwmcon, enables pwm function and pwm period length, which is the number of clock cycles for one pwm period, as shown in the table below. the other register, pwmduty, controls the duty cycle of the pwm output signal. when this register is written, the pwm signal will change immediately to the new value. this can result in 4 transitions within one pwm period, but the transition period will always have a ?dc value? between the ?old? sample and the ?new? sample. the table shows how pwm frequency (or period length) and pwm duty cycle are controlled by the settings in the two pwm sfr-registers. for a crystal frequency of 16 mhz, pwm frequency range will be about 1-253 khz. pwmcon[7:6] (number of bits) pwm frequency pwmduty (duty cycle) 00 (0) 0 (pwm module inactive) 0 01 (6) [ ] ( ) 1 0 : 5 63 1 + pwmcon f xo [ ] 63 0 : 5 pwmduty 10 (7) [ ] ( ) 1 0 : 5 127 1 + pwmcon f xo [ ] 127 0 : 6 pwmduty 11 (8) [ ] ( ) 1 0 : 5 255 1 + pwmcon f xo 255 pwmduty table 34 pwm frequency and duty-cucle. pwm is controlled by sfr 0xa9 and 0xaa. addr sfr (hex) r/w #bit init (hex) name function a9 r/w 8 0 pwmcon pwm control register 7-6: enable / period length select 00: disable pwm 01: period length is 6 bit 10: period length is 7 bit 11: period length is 8 bit 5-0: pwm frequency prescale factor (see table above) aa r/w 8 0 pwmduty pwm duty cycle (6 to 8 bits according to period length) table 35 pwm control registers - sfr 0xa9 and 0xaa.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 45 of 104 june 2004 15 interrupts nrf9e5 supports the following interrupt sources: interrupt signal natural priority interupt vector flag enable control description int0_n 1 0x03 tcon.1 ie.0 ip.0 external interrupt, active low, configurable as edge- sensitive or level-sensitive, at port p0.3 tf0 2 0x0b tcon.5 ie.1 ip.1 timer 0 interrupt int1_n 3 0x13 tcon.3 ie.2 ip.2 external interrupt, active low, configurable as edge- sensitive or level-sensitive, at port p0.4 tf1 4 0x1b tcon.7 ie.3 ip.3 timer 1 interrupt ti or ri 5 0x23 scon.0 (ri), scon.1 (ti) ie.4 ip.4 receive/transmit interrupt from serial port tf2 or exf2 6 0x2b t2con.7 (tf2), t2con.6 (exf2) ie.5 ip.5 timer 2 interrupt int2 8 0x43 exif.4 eie.0 eip.0 internal adc eoc (end of ad conversion) interrupt int3 9 0x4b exif.5 eie.1 eip.1 internal spi ready interrupt int4 10 0x53 exif.6 eie.2 eip.2 internal radio data ready (dr) interrupt int5 11 0x5b exif.7 eie.3 eip.3 internal radio address match (am) interrupt wdti 12 0x63 eicon.3 eie.4 eip.4 internal wakeup (gpio wakeup and rtc timer) interrupt table 36 nrf9e5 interrupt sources. 15.1 interrupt sfrs the following sfrs are associated with interrupt control: - ie ? sfr 0xa8 ( table 37 ) - ip ? sfr 0xb8 ( table 38 ) - exif ? sfr 0x91 ( table 39 ) - eicon ? sfr 0xd8 ( table 40 ) - eie ? sfr 0xe8 ( table 41 ) - eip ? sfr 0xf8 ( table 42 ) the ie and ip sfrs provide interrupt enable and priority control for the standard interrupt unit, as with industry standard 8051. the exif, eicon, eie, and eip registers provide flags, enable control, and priority control for the extended interrupt unit.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 46 of 104 june 2004 table 37 explains the bit functions of the ie register . bit function ie.7 ea - global interrupt enable. controls masking of all interrupts. ea = 0 disables all interrupts (ea overrides individual interrupt enable bits). when ea = 1, each interrupt is enabled or masked by its individual enable bit. ie.6 reserved. read as 0. ie.5 et2 - enable timer 2 interrupt. et2 = 0 disables timer 2 interrupt (tf2). et2 = 1 enables interrupts generated by the tf2 or exf2 flag. ie.4 es - enable serial port interrupt. es = 0 disables serial port interrupts (ti and ri). es = 1 enables interrupts generated by the ti or ri flag. ie.3 et1 - enable timer 1 interrupt. et1 = 0 disables timer 1 interrupt (tf1). et1 = 1 enables interrupts generated by the tf1 flag. ie.2 ex1 - enable external interrupt 1. ex1 = 0 disables external interrupt 1 (int1_n). ex1 = 1 enables interrupts generated by the int1_n pin. ie.1 et0 - enable timer 0 interrupt. et0 = 0 disables timer 0 interrupt (tf0). et0 = 1 enables interrupts generated by the tf0 flag. ie.0 ex0 - enable external interrupt 0. ex0 = 0 disables external interrupt 0 (int0_n). ex0 = 1 enables interrupts generated by the int0_n pin. table 37 ie register ? sfr 0xa8. table 38 explains the bit functions of the ip register . bit function ip.7 reserved. read as 1. ip.6 reserved. read as 0. ip.5 pt2 - timer 2 interrupt priority control. pt2 = 0 sets timer 2 interrupt (tf2) to low priority. pt2 = 1 sets timer 2 interrupt to high priority. ip.4 ps - serial port interrupt priority control. ps = 0 sets serial port interrupt (ti or ri) to low priority. ps = 1 sets serial port interrupt to high priority. ip.3 pt1 - timer 1 interrupt priority control. pt1 = 0 sets timer 1 interrupt (tf1) to low priority. pt1 = 1 sets timer 1 interrupt to high priority. ip.2 px1 - external interrupt 1 priority control. px1 = 0 sets external interrupt 1 (int1_n) to low priority. pt1 = 1 sets external interrupt 1 to high priority. ip.1 pt0 - timer 0 interrupt priority control. pt0 = 0 sets timer 0 interrupt (tf0) to low priority. pt0 = 1 sets timer 0 interrupt to high priority. ip.0 px0 - external interrupt 0 priority control. px0 = 0 sets external interrupt 0 (int0_n) to low priority. pt0 = 1 sets external interrupt 0 to high priority. table 38 ip register ? sfr 0xb8.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 47 of 104 june 2004 table 39 explains the bit functions of the exif register. bit function exif.7 ie5 - interrupt 5 flag. ie5 = 1 indicates that a rising edge was detected on the radio am signal (see p2). ie5 must be cleared by software. setting ie5 in software generates an interrupt, if enabled. exif.6 ie4 - interrupt 4 flag. ie4 = 1 indicates that a rising edge was detected on the radio dr signal (see p2). ie4 must be cleared by software. setting ie4 in software generates an interrupt, if enabled. exif.5 ie3 - interrupt 3 flag. ie3 = 1 indicates that the internal spi module has sent or received 8 bits, and is ready for a new command. ie3 must be cleared by software. setting ie3 in software generates an interrupt, if enabled. exif.4 ie2 - interrupt 2 flag. ie2 = 1 indicates that a rising edge was detected on the adc?s eoc signal (see chapter 10 ). ie2 must be cleared by software. setting ie2 in software generates an interrupt, if enabled. exif.3 reserved. read as 1. exif.2-0 reserved. read as 0. table 39 exif register ? sfr 0x91. table 40 explains the bit functions of the eicon register. bit function eicon.7 not used. eicon.6 reserved. read as 1. eicon.5 reserved. read as 0. eicon.4 reserved. read as 0. eicon.3 wdti - wakeup (gpio wakeup and rtc timer) interrupt flag. wdti = 1 indicates a wakeup event interrupt was detected. wdti must be cleared by software before exiting the interrupt service routine. otherwise, the interrupt occurs again. setting wdti in software generates a wakeup event interrupt, if enabled. eicon.2-0 reserved. read as 0. table 40 eicon register ? sfr 0xd8. table 41 explains the bit functions of the eie register. bit function eie.7-5 reserved. read as 1. eie.4 ewdi - enable rtc wakeup timer interrupt. ewdi = 0 disables wakeup timer interrupt (wdti). ewdi = 1 enables interrupts generated by wakeup. eie.3 ex5 - enable interrupt 5. ex5 = 0 disables interrupt 5 (radio am (address match)). ex5 = 1 enables interrupts generated by the radio am signal. eie.2 ex4 - enable interrupt 4. ex4 = 0 disables interrupt 4 (radio dr (data ready)). ex4 = 1 enables interrupts generated by the radio dr signal. eie.1 ex3 - enable interrupt 3. ex3 = 0 disables interrupt 3 (spi ready). ex3 = 1 enables interrupts generated by the spi ready signal. eie.0 ex2 - enable interrupt 2. ex2 = 0 disables interrupt 2 (adc eoc). ex2 = 1 enables interrupts generated by the adc eoc signal. table 41 eie register ? sfr 0xe8.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 48 of 104 june 2004 table 42 explains the bit functions of the eip register. bit function eip.7-5 reserved. read as 1. eip.4 pwdi - wakeup interrupt priority control. wdpi = 0 sets the wakeup interrupt (wdti) to low priority. ps = 1 sets wakeup timer interrupt to high priority. eip.3 px5 - interrupt 5 priority control. px5 = 0 sets interrupt 5 (radio am) to low priority. px5 = 1 sets interrupt 5 to high priority. eip.2 px4 - interrupt 4 priority control. px4 = 0 sets interrupt 4 (radio dr) to low priority. px4 = 1 sets interrupt 4 to high priority. eip.1 px3 - interrupt 3 priority control. px3 = 0 sets interrupt 3 (spi ready) to low priority. px3 = 1 sets interrupt 3 to high priority. eip.0 px2 - interrupt 2 priority control. px2 = 0 sets interrupt 2 (adc eoc) to low priority. px2 = 1 sets interrupt 2 to high priority. table 42 eip register ? sfr 0xf8. 15.2 interrupt processing when an enabled interrupt occurs, the cpu vectors to the address of the interrupt service routine (isr) associated with that interrupt, as listed in table 36 . the cpu executes the isr to completion unless another interrupt of higher priority occurs. each isr ends with an reti (return from interrupt) instruction. after executing the reti, the cpu returns to the next instruction that would have been executed if the interrupt had not occurred. an isr can only be interrupted by a higher priority interrupt. that is, an isr for a low- level interrupt can be interrupted only by a high-level interrupt. the cpu always completes the instruction in progress before servicing an interrupt. if the instruction in progress is reti, or a write access to any of the ip, ie, eip, or eie sfrs, the cpu completes one additional instruction before servicing the interrupt. 15.3 interrupt masking the ea bit in the ie sfr (ie.7) is a global enable for all interrupts. when ea = 1, each interrupt is enabled/masked by its individual enable bit. when ea = 0, all interrupts are masked. table 36 provides a summary of interrupt sources, flags, enables, and priorities. 15.4 interrupt priorities there are two stages of interrupt priority assignment: interrupt level and natural priority. the interrupt level (high, or low) takes precedence over natural priority. all interrupts can be assigned either high or low priority. in addition to an assigned priority level (high or low), each interrupt has a natural priority, as listed in table 36 . simultaneous interrupts with the same priority level (for example, both high) are resolved according to their natural priority. for example, if int0_n and int2 are both programmed as high priority, int0_n takes precedence. once an interrupt is being serviced, only an interrupt of higher priority level can interrupt the service routine of the interrupt currently being serviced.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 49 of 104 june 2004 15.5 interrupt sampling the internal timers and serial port generate interrupts by setting their respective sfr interrupt flag bits. the cpu samples external interrupts once per instruction cycle, at the rising edge of cpu_clk at the end of cycle c4. the int0_n and int1_n signals are both active low and can be programmed through the it0 and it1 bits in the tcon sfr to be either edge-sensitive or level-sensitive. for example, when it0 = 0, int0_n is level-sensitive and the cpu sets the ie0 flag when the int0_n pin is sampled low. when it0 = 1, int0_n is edge-sensitive and the cpu sets the ie0 flag when the int0_n pin is sampled high then low on consecutive samples. to ensure that edge-sensitive interrupts are detected, the corresponding ports should be held high for four clock cycles and then low for four clock cycles. level- sensitive interrupts are not latched and must remain active until serviced.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 50 of 104 june 2004 15.6 interrupt latency interrupt response time depends on the current state of the cpu. the fastest response time is five instruction cycles: one to detect the interrupt, and four to perform the lcall to the isr. the maximum latency (thirteen instruction cycles) occurs when the cpu is currently executing an reti instruction followed by a mul or div instruction. the thirteen instruction cycles in this case are: one to detect the interrupt, three to complete the reti, five to execute the div or mul, and four to execute the lcall to the isr. for the maximum latency case, the response time is 13 x 4 = 52clock cycles. 15.7 interrupt latency from power down state. the nrf9e5 may be set into power down state by writing a non zero value to sfr 0xb6, register ck_ctrl. the cpu will then perform a controlled shutdown of clock and power regulator depending on what mode was selected. the system can only be restarted from an rtc wakeup, a gpio wakeup or a watchdog reset. if a wakeup interrupt is enabled, the startup time for regulators and clocks will be added to the interrupt latency. see 17.2.1 startup time from reset 15.8 single-step operation the nrf9e5 interrupt structure provides a way to perform single-step program execution. when exiting an isr with an reti instruction, the cpu will always execute at least one instruction of the task program. therefore, once an isr is entered, it cannot be re-entered until at least one program instruction is executed. to perform single-step execution, program one of the external interrupts (for example, int0_n) to be level sensitive and write an isr for that interrupt that terminates as follows: jnb tcon.1,$ ; wait for high on int0_n jb tcon.1,$ ; wait for low on int0_n reti ; return for isr the cpu enters the isr when int0_n goes low, then waits for a pulse on int0_n. each time int0_n is pulsed, the cpu exits the isr, executes one program instruction, then re-enters the isr.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 51 of 104 june 2004 16 lf clock wakeup functions and watchdog 16.1 the lf clock the nrf9e5 contains has an internal low frequency clock cklf that is always active. when the crystal oscillator clocks the circuit, the cklf is a 4khz clock derived from the crystal oscillator (provided the cklfcon register is set according to crystal frequency and prescaler. xof and up_clk_freq respectively, see table 22 ). when no crystal oscillator clock is available, the cklf is a low power rc oscillator (lp_osc) that cannot be disabled, so it will run continuously as long as vdd = 1.8v. the microprocessor can determine the phase of the cklf clock by reading ck_ctrl sfr 0xb6, see table 50 . 16.2 tick calibration the ?tick? is an interval (in cklf periods) that determines the resolution of the watchdog and the rtc wakeup timer. the tick is nominally 1ms (4 cklf cycles). when the cpu is active and in power down modes where the chip still has crystal clock, the ?tick? will be as accurate as the crystal oscillator. when the cklf switches to the rc oscillator (lp_osc) in deep power down modes, the tick will no longer be accurate. the lp_osc clock source is very inaccurate, and may vary from 0.5ms to 3ms depending production lot, temperature and supply voltage. that means that watchdog and rtc wakeup may not be used for any accurate timing functions if these power down modes are used. the accuracy can be improved by calibrating the tick value at regular intervals. the register tick_dv controls how many lp_osc periods elapse between each tick. the frequency of the lp_osc (between 1 khz and 5 khz) can be measured by timer2 in capture mode with t2ex enabled (exen2=1). the signal connected to t2ex has exactly half the frequency of lp_osc. the 16-bit difference between two consecutive captures in sfr-registers{rcap2h,rcap2l} is proportional to the lp_osc period. for details about timer2 see ch. 18.8.3 and figure 21 timer 2 ? timer/counter with capture tick is controlled by sfrs 0xb5 and 0xbf addr sfr r/w #bit init hex name function b5 r/w 8 03 tick_dv divider that?s used in generating tick from cklf frequency. t tick = (1 + tick_dv) / f cklf the default value gives a tick of 1ms nominal as default (with cklf derived from crystal oscillator). bf r/w 6 27 cklfcon configure cklf generation with crystal frequency and prescaler value. note this register only controls the generation of cklf, not the actual prescaler values. 5-3: should be set equal to xof, table 22 2: should be set equal to up_clk_en, table 22 1-0: should be set equal to up_clk_freq, table 22 table 43 tick control register - sfr 0xb5.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 52 of 104 june 2004 16.3 rtc wakeup timer the rtc is a simple 24 bit down counter that produces an optional interrupt and reloads automatically when the count reaches zero. this process is initially disabled, and will be enabled with the first write to the lower 16 bit of the timer latch. writing the lower 16 bits of the timer latch will always be followed by a reload of the counter. writing the upper 8 bit of the timer latch should only be done when the timer is disabled. the counter may be disabled again by writing a disable opcode to the control register. both the latch and the counter value may be read by giving the respective codes in the control register, see description in table 45 . this counter is used for a wakeup sometime in the future (a relative time wakeup call). if ?n? is written to the counter, the first wakeup will happen from somewhere between ?n+1? and ?n+2? ?tick? from the completion of the write, thereafter a new wakeup is issued every ?n+1? "tick" until the unit is disabled or another value is written to the latch. the wakeup timer is one of the sources that can generate a wdti interrupt to the cpu. the programmer may poll the eicon.3 flag or enable the interrupt. if the device is in a power down state, the wakeup will force the device to exit power down regardless of the state of eie.4 interrupt enable. the nrf9e5 do not provide any ?absolute time functions?. absolute time functions in nrf9e5 can well be handled in software since the ram is continuously powered even when in sleep mode. 16.4 programmable gpio wakeup function any number of the pins in port 0 may be used as wakeup signals for the nrf9e5. the device may be programmed to react on either rising or falling or both edges of each pin individually. additionally each pin is equipped with a programmable ?filter? that can be used for glitch suppression. debounce edge wwcon cklf p0x [1:0] [3:2] wakeup p0x figure 15 wakeup filter, each pin for gpio wakeup function. the debounce act as a low pass filter. the input has to be stable for a number of clock pulses given for the corresponding change to appear on the output. edge triggers on either positive, negative or both edges. the edge delay is 2 clock cycles. please see table 44 and table 47 for filter configuration.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 53 of 104 june 2004 filter selection debounce edge detector selection wcon [1:0] number of clock pulses wcon [3:2] pos / neg trigger 00 0 00 off 01 2 01 pos 10 8 10 neg 11 64 11 both table 44 gpio wakeup filter configuration. 16.5 watchdog the watchdog is activated on the first write to its control register sfr 0xad. it can not be disabled by any other means than a reset. the watchdog register is loaded by writing a 16-bit value to the two 8-bit data registers (sfr 0xab and 0xac) and then the writing the correct opcode to the control register. the watchdog will then count down towards 0 and when 0 is reached the complete microcontroller will be reset to avoid the reset, the software must load new values into the watchdog register sufficiently often. 16.6 programming interface to watchdog and wakeup functions figure 16 shows how the blocks that are always active are connected to the cpu. rtc timer gpio wakeup and watchdog are controlled via sfrs 0xab, 0xac and 0xad. these 3 registers regx_msb, regx_lsb and regx_ctrl are used to interface the blocks running on the slow cklf clock. the 16-bit register {regx_msb, regx_lsb} can be written or read as two bytes from the cpu.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 54 of 104 june 2004 typical sequences are: write: wait until regx_crtl.4 == 0 (i.e. not busy) write regx_msb, write regx_lsb, write regx_ctrl read: wait until regx_crtl.4 == 0 (i.e. not busy) write regx_ctrl, wait until regx_crtl.4 == 0 (i.e. not busy) read regx_msb, read regx_lsb note : please wait until not busy before accessing sfr 0xb6 ck_ctrl (page 58 ) tick wakeup int watchdog_reset 8+16-bit register timer_latch 8-bit cpu register regx_lsb 8-bit cpu register regx_msb 8-bit cpu register regx_ctrl load 16-bit bus 24-bit down counter zero load 16-bit down counter zero load ce gpio wakeup io rtc int p1 gpio ce load clocked on cpu clock clocked on cklf figure 16 block diagram of wakeup and watchdog function. table 45 below describe the functions of the sfr registers that control these blocks, and table 46 and table 47 explains the contents of the individual control registers for watchdog and wakeup functions. addr sfr (hex) r/w #bit init hex name function ab r/w 8 00 regx_msb most significant part of 16 bit register for interface to watchdog, rtc timer and gpio wakeup ac r/w 8 00 regx_lsb least significant part of 16 bit register for interface to watchdog, rtc timer and gpio wakeup ad r/w 5 00 regx_ctrl control for 16 bit register for transfers to and from watchdog, rtc timer and gpio wakeup. 4: regx interface busy (read only). 3: read (0) / write (1) 2-0: indirect address, see leftmost column in table 46 table 45 wakeup, rtc timer and watchdog sfr-registers.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 55 of 104 june 2004 addr ctrl [2:0] r/w ctrl [3] #bit init hex name function 0 16 0000 rwd watchdog register (count) 0 1 16 0000 wwd watchdog register (count) 0 16 0000 rgtimer 15-8: msb part of rtc counter 7-0: msb part of rtc latch 1 1 12 000 wgtimer 11-8: gtimer latch 7-0: msb part of rtc latch 0 16 0000 rrtclat least significant part of rtc latch 2 1 16 0000 wrtclat least significant part of rtc latch 0 16 0000 rrtc rtc counter value 3 1 0 - wrtcdis disable rtc (data not used) 0 9 000 rwsta0 wakeup status bit 8: rtc timer status 7-0: wakeup status for pins p07-p00 4 1 16 0000 wwcon0 gpio wakeup configuration for p03-p00. see table 47 . 0 9 000 rwsta1 wakeup status (identical to wsta0) 5 1 16 0000 wwcon1 gpio wakeup configuration for p07-p04. see table 47 . table 46 indirect addresses and functions. bits wwcon1 function wwcon0 unction 15:14 edge selection for p07 edge selection for p03 13:12 edge filter for p07 edge filter for p03 11:10 edge selection for p06 edge selection for p02 9:8 edge filter for p06 edge filter for p02 7:6 edge selection for p05 edge selection for p01 5:4 edge filter for p05 edge filter for p01 3:2 edge selection for p04 edge selection for p00 1:0 edge filter for p04 edge filter for p00 table 47 bit fields in register wwcon1 and wwcon0. 16.7 reset the nrf9e5 can be reset either by the on-chip power-on reset circuitry or by the on- chip watchdog counter. 16.7.1 power-on reset the power-on reset circuitry keeps the chip in power-on-reset state until the supply voltage reaches vddmin (a voltage, less than 1.9v sufficiently high for digital operation). at this point the internal voltage generators and oscillators start up, the sfrs are initialized to their reset values, as listed in table 62 , and thereafter the cpu begins program execution at the standard reset vector address 0x0000. the startup time from power-on reset is normally determined by both the crystal oscillator startup time and the frequency of the low power oscillator (lp_osc). this total may vary from 1 to 3 ms depending on processing, temperature and supply voltage.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 56 of 104 june 2004 16.7.2 watchdog reset if the watchdog reset signal goes active, nrf9e5 enters the same reset sequence as for power-on reset. that is, the internal voltage generators and oscillators start up, the sfrs are initialized to their reset values, as listed in table 62 , and thereafter the cpu begins program execution at the standard reset vector address 0x0000. the startup time from watchdog reset is somewhat shorter; expect a variation from 0.4 to 2ms depending on processing, temperature and supply voltage. 16.7.3 program reset address the program reset address is controlled by the rstreas register, sfr 0xb1, see table 48 this register shows which reset source that caused the last reset, and provides a choice of two different program start addresses. the default value is power-on reset, which starts the boot loader, while a watchdog reset does not reboot and restarts at address 0 of the already loaded program. addr sfr (hex) r/w #bit init (hex) name function b1 r/w 2 02 rstreas bit 0: reason for last reset 0: por 1: any other reset source clear this bit in software to force a reboot after jump to zero (boot loader will load code ram if this bit is 0) bit 1: use irom for reset vector 0: reset vectors to 0x0000. 1: reset vectors to 0x8000. table 48 reset control register - sfr 0xb1.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 57 of 104 june 2004 17 power saving modes nrf9e5 provides the two industry standard 8051 power saving modes: idle mode and stop mode. to achieve more power saving several additional power-down modes are provided, where both oscillator and internal power regulators may be turned off. the bits that control entry into idle and stop modes are in the pcon register at sfr address 0x87, listed in table 49 . the bits that control entry into power down mode are in the ck_ctrl register at sfr address 0xb6, listed in table 51 . bit function pcon.7 smod ? serial port baud-rate doubler enable. when smod = 1, the baud rate for serial port is doubled. pcon.6?4 reserved. pcon.3 gf1 ? general purpose flag 1. bit-addressable, general purpose flag for software control. pcon.2 gf0 ? general purpose flag 0. bit-addressable, general purpose flag for software control. pcon.1 stop ? stop mode select. setting the stop bit places the nrf9e5 in stop mode. pcon.0 idle ? idle mode select. setting the idle bit places the nrf9e5 in idle mode. table 49 pcon register ? sfr 0x87. 17.1 standard 8051 power saving modes 17.1.1 idle mode an instruction that sets the idle bit (pcon.0) causes the nrf9e5 to enter idle mode when that instruction completes. in idle mode, cpu processing is suspended and internal registers and memory maintain their current data. however, unlike the standard 8051, the cpu clock is not disabled internally, thus not much power is saved. there are two ways to exit idle mode: activate any enabled interrupt or watchdog reset. activation of any enabled interrupt causes the hardware to clear the idle bit and terminate idle mode. the cpu executes the isr associated with the received interrupt. the reti instruction at the end of the isr returns the cpu to the instruction following the one that put the nrf9e5 into idle mode. a watchdog reset causes the nrf9e5 to exit idle mode, reset internal registers, execute its reset sequence and begin program execution at the standard reset vector address 0x0000. 17.1.2 stop mode an instruction that sets the stop bit (pcon.1) causes the nrf9e5 to enter stop mode when that instruction completes. stop mode is identical to idle mode, except that the only way to exit stop mode is by watchdog reset since there is little power saving, stop mode is not recommended, as it is more efficient to use power down mode.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 58 of 104 june 2004 17.2 additional power down modes an instruction that sets the ck_ctrl ( sfr 0xb6) to a non zero value causes the nrf9e5 to enter power down mode when that instruction completes. in power down mode, cpu processing is suspended, while internal registers and memories maintain their current data. the cpu will perform a controlled shutdown of clock and power regulators as requested by ck_ctrl. the device can only be restarted from an event on a p0 gpio pin, an rtc wakeup or a watchdog reset. activation of any enabled wakeup source causes the hardware to clear the ck_ctrl bit and terminate power down mode. if there is an enabled interrupt associated with the wakeup even, the cpu executes the isr associated with that interrupt immediately after power and clocks are restored. the reti instruction at the end of the isr returns the cpu to the instruction following the one that put the nrf9e5 into power down mode. a watchdog reset causes the nrf9e5 to exit power down mode, reset internal registers, execute its reset sequence and begin program execution at the standard reset vector address 0x0000. addr sfr r/w #bit init hex name function w 3 0 ck_ctrl set power down according to table 51 . b6 r 1 - ck_ctrl read lfck clock in lsb. other bits are unpredictable. table 50 ck_ctrl register ? sfr 0xb6. note: before writing the ck_ctrl register, make sure that the busy bit of rtc/watchdog sfr 0xad, bit 4 (page 54 ) is not set note: when using power down modes where the cklf source is lp_osc, the startup time may be so long that the cpu may loose the corresponding interrupt. ck_ctrl (write) function cklf source xtal osc typical current typical startup 000 normal operation, active xtal on 1 ma - 001 light power down xtal on 0.4 ma 2.5 s 010 moderate power down xtal on 125 a 7 s 011 standby mode lp_osc on 25 a 150 s 1-- deep power down lp_osc off 2.5 a 1000 s table 51 power down modes. the table above shows typical startup time from interrupt. for gpio the debounce time must be added, but during debounce the device is still in power down. 17.2.1 startup time from reset startup time consists of a number of lp_osc cycles + a number of xtal clock cycles. f lp_osc may vary from 1 to 5.5khz over voltage and temperature.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 59 of 104 june 2004 startup times are summarized in the table below: reason of startup phase i (power and clock) phase ii (initialization and synchronization) power on xo start-up time (3ms max) the longest of: 2500 f xtal cycles 0-1 lp_osc cycles watchdog xo start-up time if not already running the longest of: 2500 f cpu cycles 0-1 lp_osc cycles table 52 startup times from power down mode.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 60 of 104 june 2004 18 microcontroller the embedded microcontroller is the dw8051 macrocell from synopsys which is similar to the dallas ds80c320 in terms of hardware features and instruction-cycle timing. 18.1 memory organization boot loader program/data memory. accessible with movc and movx. 0000h 0fffh 8000h 81ffh ffffh accessible by direct and indirect addressing. accessible by direct addressing only. accessible by indirect addressing only. internal data memory 00h 7fh 80h ffh ffh 80h special function registers upper 128 bytes. lower 128 bytes. program memory/data memory (eram) iram sfr figure 17 memory map and organization. 18.1.1 program memory/data memory the nrf9e5 has 4kb of program memory available for user programs located at the bottom of the address space as shown in figure 17 . this memory also function as a random access memory and can be accessed with the movx and movc instructions. after power on reset the boot loader loads the user program from the external serial eeprom and stores it from address 0 in this memory. 18.1.2 internal data memory the internal data memory, illustrated in figure 17 , consists of: 128 bytes of registers and scratchpad memory accessible through direct or indirect addressing (addresses 0x00?0x7f). 128 bytes of scratchpad memory accessible through indirect addressing (0x80? 0xff). 128 special function registers (sfrs) accessible through direct addressing. the lower 32 bytes form four banks of eight registers (r0?r7). two bits on the program status word (psw) select which bank is in use. the next sixteen bytes form a block of bit-addressable memory space at bit addresses 0x00?0x7f. all of the bytes in the lower 128 bytes are accessible through direct or indirect addressing. the sfrs and the upper 128 bytes of ram share the same address range (0x80-0xff). however, the actual address space is separate and is differentiated by the type of addressing. direct
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 61 of 104 june 2004 addressing accesses the sfrs, while indirect addressing accesses the upper 128 bytes of ram. most sfrs are reserved for specific functions, as described in 18.6 special function registers on page 69 . sfr addresses ending in 0h or 8h are bit-addressable. 18.2 program format in external eeprom the table below shows the layout of the first few bytes of the eeprom image. 7 6 5 4 3 2 1 0 0: version (now 00) reserved (now 00) speed xo_freq 1: offset to start of user program (n) 2: number of 256 byte blocks in user program (includes block 0 that is not full) ? optional user data, not interpreted by boot loader ? ? n: first byte of user program, goes into eram at 0x0000 n+1: second byte of user program, goes into eram at 0x0001 ? table 53 eeprom layout. the contents of the 4 lowest bits in the first byte is used by the boot loader to set the correct spi frequency. these fields are encoded as shown below: speed (bit 3): eeprom max speed 0 = 1mhz 1 = 0.5mhz xo_freq (bits 2,1 and 0): crystal oscillator frequency 000 = 4mhz, 001 = 8mhz, 010 = 12mhz, 011 = 16mhz, 100 = 20mhz the program eeprep 1 can be used to add this header to a program file. command format: eeprep [options] is the output file of an assembler or compiler is a file suitable for programming the eeprom (above format with no user data). both files are ?intelhex? format. the options available for eeprep are: -c n set crystal fr equency in mhz. -i ignore checksums -p n set program memory size (default 4096 bytes) -s select slow eeprom clock (500khz) 1 available on www.nordicsemi.no
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 62 of 104 june 2004 18.3 instruction set all nrf9e5 instructions are binary-code?compatible and perform the same functions that they do in the industry standard 8051. the effects of these instructions on bits, flags, and other status functions is identical to the industry-standard 8051. however, the timing of the instructions is different, both in terms of number of clock cycles per instruction cycle and timing within the instruction cycle. table 55 to table 60 lists the nrf9e5 instruction set and the number of instruction cycles required to complete each instruction. symbol function a accumulator rn register r0?r7 direct internal register address @ri internal register pointed to by r0 or r1 (except movx) rel two?s complement offset byte bit direct bit address #data 8-bit constant #data 16 16-bit constant addr 16 16-bit destination address addr 11 11-bit destination address table 54 legend for instruction set table. table 55 to table 60 define the symbols and mnemonics used in table 54 .
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 63 of 104 june 2004 arithmetic instructions mnemonic description byte instr. cycles hex code add a, rn add register to a 1 1 28?2f add a, direct add direct byte to a 2 2 25 add a, @ri add data memory to a 1 1 26?27 add a, #data add immediate to a 2 2 24 addc a, rn add register to a with carry 1 1 38?3f addc a, direct add direct byte to a with carry 2 2 35 addc a, @ri add data memory to a with carry 1 1 36?37 addc a, #data add immediate to a with carry 2 2 34 subb a, rn subtract register from a with borrow 1 1 98?9f subb a, direct subtract direct byte from a with borrow 2 2 95 subb a, @ri subtract data memory from a with borrow 1 1 96?97 subb a, #data subtract immediate from a with borrow 2 2 94 inc a increment a 1 1 04 inc rn increment register 1 1 08?0f inc direct increment direct byte 2 2 05 inc @ri increment data memory 1 1 06?07 dec a decrement a 1 1 14 dec rn decrement register 1 1 18?1f dec direct decrement direct byte 2 2 15 dec @ri decrement data memory 1 1 16?17 inc dptr increment data pointer 1 3 a3 mul ab multiply a by b 1 5 a4 div ab divide a by b 1 5 84 da a decimal adjust a 1 1 d4 all mnemonics are copyright ? intel corporation 1980. table 55 nrf9e5 instruction set, arithmetic instructions.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 64 of 104 june 2004 logical instructions mnemonic description byte instr. cycles hex code anl a, rn and register to a 1 1 58?5f anl a, direct and direct byte to a 2 2 55 anl a, @ri and data memory to a 1 1 56?57 anl a, #data and immediate to a 2 2 54 anl direct, a and a to direct byte 2 2 52 anl direct, #data and immediate data to direct byte 3 3 53 orl a, rn or register to a 1 1 48?4f orl a, direct or direct byte to a 2 2 45 orl a, @ri or data memory to a 1 1 46?47 orl a, #data or immediate to a 2 2 44 orl direct, a or a to direct byte 2 2 42 orl direct, #data or immediate data to direct byte 3 3 43 xrl a, rn exclusive-or register to a 1 1 68?6f xrl a, direct exclusive-or direct byte to a 2 2 65 xrl a, @ri exclusive-or data memory to a 1 1 66?67 xrl a, #data exclusive-or immediate to a 2 2 64 xrl direct, a exclusive-or a to direct byte 2 2 62 xrl direct, #data exclusive-or immediate to direct byte 3 3 63 clr a clear a 1 1 e4 cpl a complement a 1 1 f4 swap a swap nibbles of a 1 1 c4 rl a rotate a left 1 1 23 rlc a rotate a left through carry 1 1 33 rr a rotate a right 1 1 03 rrc a rotate a right through carry 1 1 13 all mnemonics are copyright ? intel corporation 1980. table 56 nrf9e5 instruction set, logical instructions.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 65 of 104 june 2004 boolean instructions mnemonic description byte instr. cycles hex code clr c clear carry 1 1 c3 clr bit clear direct bit 2 2 c2 setb c set carry 1 1 d3 setb bit set direct bit 2 2 d2 cpl c complement carry 1 1 b3 cpl bit complement direct bit 2 2 b2 anl c, bit and direct bit to carry 2 2 82 anl c, /bit and direct bit inverse to carry 2 2 b0 orl c, bit or direct bit to carry 2 2 72 orl c, /bit or direct bit inverse to carry 2 2 a0 mov c, bit move direct bit to carry 2 2 a2 mov bit, c move carry to direct bit 2 2 92 all mnemonics are copyright ? intel corporation 1980. table 57 nrf9e5 instruction set, boolean instructions.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 66 of 104 june 2004 data transfer instructions mnemonic description byte instr. cycles hex code mov a, rn move register to a 1 1 e8?ef mov a, direct move direct byte to a 2 2 e5 mov a, @ri move data memory to a 1 1 e6?e7 mov a, #data move immediate to a 2 2 74 mov rn, a move a to register 1 1 f8?ff mov rn, direct move direct byte to register 2 2 a8?af mov rn, #data move immediate to register 2 2 78?7f mov direct, a move a to direct byte 2 2 f5 mov direct, rn move register to direct byte 2 2 88?8f mov direct, direct move direct byte to direct byte 3 3 85 mov direct, @ri move data memory to direct byte 2 2 86?87 mov direct, #data move immediate to direct byte 3 3 75 mov @ri, a move a to data memory 1 1 f6?f7 mov @ri, direct move direct byte to data memory 2 2 a6?a7 mov @ri, #data move immediate to data memory 2 2 76?77 mov dptr, #data move immediate to data pointer 3 3 90 movc a, @a+dptr move code byte relative dptr to a 1 3 93 movc a, @a+pc move code byte relative pc to a 1 3 83 movx a, @ri move external data (a8) to a 1 2?9* e2?e3 movx a, @dptr move external data (a16) to a 1 2?9* e0 movx @ri, a move a to external data (a8) 1 2?9* f2?f3 movx @dptr, a move a to external data (a16) 1 2?9* f0 push direct push direct byte onto stack 2 2 c0 pop direct pop direct byte from stack 2 2 d0 xch a, rn exchange a and register 1 1 c8?cf xch a, direct exchange a and direct byte 2 2 c5 xch a, @ri exchange a and data memory 1 1 c6?c7 xchd a, @ri exchange a and data memory nibble 1 1 d6?d7 all mnemonics are copyright ? intel corporation 1980. table 58 nrf9e5 instruction set, data transfer instructions. * number of cycles is 2 + ckcon.2-0. (ckcon.2-0 is the integer value of the 3lsb of sfr 0x8e ckcon). default is 3 cycles.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 67 of 104 june 2004 branching instructions mnemonic description byte instr. cycles hex code acall addr 11 absolute call to subroutine 2 3 11?f1 lcall addr 16 long call to subroutine 3 4 12 ret return from subroutine 1 4 22 reti return from interrupt 1 4 32 ajmp addr 11 absolute jump unconditional 2 3 01?e1 ljmp addr 16 long jump unconditional 3 4 02 sjmp rel short jump (relative address) 2 3 80 jc rel jump on carry = 1 2 3 40 jnc rel jump on carry = 0 2 3 50 jb bit, rel jump on direct bit = 1 3 4 20 jnb bit, rel jump on direct bit = 0 3 4 30 jbc bit, rel jump on direct bit = 1 and clear 3 4 10 jmp @a+dptr jump indirect relative dptr 1 3 73 jz rel jump on accumulator = 0 2 3 60 jnz rel jump on accumulator /= 0 2 3 70 cjne a, direct, rel compare a, direct jne relative 3 4 b5 cjne a, #d, rel compare a, immediate jne relative 3 4 b4 cjne rn, #d, rel compare reg, immediate jne relative 3 4 b8?bf cjne @ri, #d, rel compare ind, immediate jne relative 3 4 b6?b7 djnz rn, rel decrement register, jnz relative 2 3 d8?df djnz direct, rel decrement direct byte, jnz relative 3 4 d5 all mnemonics are copyright ? intel corporation 1980. table 59 nrf9e5 instruction set, branching instructions. miscellaneous instructions mnemonic description byte instr. cycles hex code nop no operation 1 1 00 there is an additional reserved opcode (a5) that will also act as a nop. all mnemonics are copyright ? intel corporation 1980. table 60 nrf9e5 instruction set, miscellaneous instructions.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 68 of 104 june 2004 18.4 instruction timing instruction cycles in the nrf9e5 are four clock cycles in length, as opposed to twelve clock cycles per instruction cycle in the standard 8051. this translates to a 3x improvement in execution time for most instructions. however, some instructions require a different number of instruction cycles on the nrf9e5 than they do on the standard 8051. in the standard 8051, all instructions except for mul and div take one or two instruction cycles to complete. in the nrf9e5 architecture, instructions can take between one and five instruction cycles to complete. for example, in the standard 8051, the instructions movx a, @dptr and mov direct, direct each take two instruction cycles (twenty-four clock cycles) to execute. in the nrf9e5 architecture, movx a, @dptr takes two instruction cycles (eight clock cycles) and mov direct, direct takes three instruction cycles (twelve clock cycles). both instructions execute faster on the nrf9e5 than they do on the standard 8051, but require different numbers of clock cycles. for timing of real-time events, use the numbers of instruction cycles from table 55 to table 60 to calculate the timing of software loops. the bytes column of these table indicates the number of memory accesses (bytes) needed to execute the instruction. in most cases, the number of bytes is equal to the number of instruction cycles required to complete the instruction. however, as indicated in table 55 , there are some instructions (for example, div and mul) that require a greater number of instruction cycles than memory accesses.by default, the nrf9e5 timer/counters run at twelve clock cycles per increment so that timer-based events have the same timing as with the standard 8051. the timers can be configured to run at four clock cycles per increment to take advantage of the higher speed of the nrf9e5. 18.5 dual data pointers the nrf9e5 employs dual data pointers to accelerate data memory block moves. the standard 8051 data pointer (dptr) is a 16-bit value used to address external data ram or peripherals. the nrf9e5 maintains the standard data pointer as dptr0 at sfr locations 0x82 and 0x83. it is not necessary to modify code to use dptr0. the nrf9e5 adds a second data pointer (dptr1) at sfr locations 0x84 and 0x85. the sel bit in the dptr select register, dps (sfr 0x86), selects the active pointer. when sel = 0, instructions that use the dptr will use dpl0 and dph0. when sel = 1, instructions that use the dptr will use dpl1 and dph1. sel is the bit 0 of sfr location 0x86. no other bits of sfr location 0x86 are used. all dptr-related instructions use the currently selected data pointer. to switch the active pointer, toggle the sel bit. the fastest way to do so is to use the increment instruction (inc dps). this requires only one instruction to switch from a source address to a destination address, saving application code from having to save source and destination addresses when doing a block move. using dual data pointers provides significantly increased efficiency when moving large blocks of data. the sfr locations related to the dual data pointers are: - 0x82 dpl0 dptr0 low byte - 0x83 dph0 dptr0 high byte - 0x84 dpl1 dptr1 low byte - 0x85 dph1 dptr1 high byte - 0x86 dps dptr select (lsb)
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 69 of 104 june 2004 18.6 special function registers the special function registers (sfrs) control several of the features of the nrf9e5. most of the nrf9e5 sfrs are identical to the standard 8051 sfrs. however, there are additional sfrs that control features that are not available in the standard 8051. table 61 lists the nrf9e5 sfrs and indicates which sfrs are not included in the standard 8051 sfr space. when writing software for the nrf9e5, use equate statements to define the sfrs that are specific to the nrf9e5 and custom peripherals. in table 61 , sfr bit positions that contain a 0 or a 1 cannot be written to and, when read, always return the value shown (0 or 1). sfr bit positions that contain ??? are available but not used. table 62 shows the value of each sfr, after power-on reset or a watchdog reset, together with a pointer to a detailled description of each register. please note that any unused address in the sfr address space is reserved and should not be written to. notes to table 61 on next page : (1) not part of standard 8051 architecture. (2) registers unique to nrf9e5 (3) p0, p1 and p3 differ from standard 8051
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 70 of 104 june 2004 addr register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x80 p0(3) port 0 0x81 sp stack pointer 0x82 dpl0 data pointer 0, low byte 0x83 dph0 data pointer 0, high byte 0x84 dpl1(1) data pointer 1, low byte 0x85 dph1(1) data pointer 1, high byte 0x86 dps(1) 0 0 0 0 0 0 0 sel 0x87 pcon smod - 1 1 gf1 gf0 stop idle 0x88 tcon tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 0x89 tmod gate c/t m1 m0 gate c/t m1 m0 0x8a tl0 timer/counter 0 value, low byte 0x8b tl1 timer/counter 1 value, low byte 0x8c th0 timer/counter 0 value, high byte 0x8d th1 timer/counter 1 value, high byte 0x8e ckcon(1) - - t2m t1m t0m md2 md1 md0 0x8f spc_fnc(1) 0 0 0 0 0 0 0 wrs 0x90 p1(3) - - - - port 1 bit 3:0 0x91 exif(1) ie5 ie4 ie3 ie2 1 0 0 0 0x92 mpage(1) - - - - - - - - 0x93 p0_drv(2) drive strength of port 0 0x94 p0_dir(2) direction of port 0 0x95 p0_alt(2) alternate functions of port 0 0x96 p1_dir(2) - - - - direction of port 1 0x97 p1_alt(2) - - - - alt.funct. of port 1 0x98 scon sm0 sm1 sm2 ren tb8 rb8 ti ri 0x99 sbuf serial port data buffer 0xa0 p2(3) am cd dr/ trx_ce eoc/ tx_en racsn sbmiso sbmosi sbsck 0xa8 ie ea 0 et2 es et1 ex1 et0 ex0 0xa9 pwmcon (2) pwm_length pwm_prescale 0xaa pwmduty (2) pwm_duty_cycle 0xab regx_msb (2) high byte of watchdog/rtc register 0xac regx_lsb (2) low byte of watchdog/rtc register 0xad regx_ctrl (2) - - - control of regx_msb and regx_lsb 0xb1 rstreas (2) - - - - - - rflr 0xb2 spi_data (2) spi_data input/output bits 0xb3 spi_ctrl (2) - - - - - spi_ctrl 0xb4 spiclk (2) - - - - spiclk 0xb5 tick_dv (2) tick_dv 0xb6 ck_ctrl (2) - - - - - ck_ctrl 0xb8 ip 1 0 pt2 ps pt1 px1 pt0 px0 0xbf cklfcon (2) - - xof up_clk _en up_clk_freq 0xc8 t2con tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl2 0xca rcap2l timer/counter 2 capture or reload, low byte 0xcb rcap2h timer/counter 2 capture or reload, high byte 0xcc tl2 timer/counter 2 value, low byte 0xcd th2 timer/counter 2 value, high byte 0xd0 psw cy ac f0 rs1 rs0 ov f1 p 0xd8 eicon(1) - 1 0 0 wdti 0 0 0 0xe0 acc accumulator register 0xe8 eie(1) 1 1 1 ewdi ex5 ex4 ex3 ex2 0xf0 b b-register 0xf8 eip(1) 1 1 1 pwdi px5 px4 px3 px2 0xfe hwrev (2) device hardware revision number 0xff ----- reserved, do not use table 61 special function registers summary.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 71 of 104 june 2004 register addr reset value description acc 0xe0 0x00 accumulator register b 0xf0 0x00 b-register ck_ctrl 0xb6 0x00 table 51 , page 58 ckcon 0x8e 0x01 table 67 , page 78 cklfcon 0xbf 0x27 table 43 on page 51 dph0 0x83 0x00 ch. 18.5 , page 68 dph1 0x85 0x00 ch. 18.5 , page 68 dpl0 0x82 0x00 ch. 18.5 , page 68 dpl1 0x84 0x00 ch. 18.5 , page 68 dps 0x86 0x00 ch. 18.5 , page 68 eicon 0xd8 0x40 table 40 , page 47 eie 0xe8 0xe0 table 41 , page 47 eip 0xf8 0xe0 table 42 , page 48 exif 0x91 0x08 table 39 , page 47 hwrev 0xfe 0x00,read only hardware revision no ie 0xa8 0x00 table 37 , page 46 ip 0xb8 0x80 table 38 , page 46 mpage 0x92 0x00 do not use p0 0x80 0xff table 10 , page 15 p0_alt 0x95 0x00 table 10 , page 15 p0_dir 0x94 0xff table 10 , page 15 p0_drv 0x93 0x00 table 10 , page 15 p1 0x90 0xff table 12 , page 16 p1_alt 0x97 0x00 table 12 , page 16 p1_dir 0x96 0xf4 table 12 , page 16 p2 0xa0 0x08 table 15 , page 19 pcon 0x87 0x30 table 49 , page 57 psw 0xd0 0x00 table 63 , page 72 pwmcon 0xa9 0x00 table 35 , page 44 pwmduty 0xaa 0x00 table 35 , page 44 rcap2h 0xcb 0x00 ch. 18.8.3.3 , page 80 rcap2l 0xca 0x00 ch. 18.8.3.3 , page 80 regx_ctrl 0xad 0x00 table 45 , page 54 regx_lsb 0xac 0x00 table 45 , page 54 regx_msb 0xab 0x00 table 45 , page 54 rstreas 0xb1 0x02 table 48 , page 56 sbuf 0x99 0x00 ch. 18.9 , page 81 scon 0x98 0x00 table 71 , page 82 sp 0x81 0x07 stack pointer spc_fnc 0x8f 0x00 do not use spi_ctrl 0xb3 0x00 table 33 , page 43 spi_data 0xb2 0x00 table 33 , page 43 spiclk 0xb4 0x00 table 33 , page 43 t2con 0xc8 0x00 table 68 , page 79 tcon 0x88 0x00 table 66 , page 75 th0 0x8c 0x00 ch. 18.8 , page 74 th1 0x8d 0x00 ch. 18.8 , page 74 th2 0xcd 0x00 ch. 18.8 , page 74 tick_dv 0xb5 0x1d table 43 , page 51 tl0 0x8a 0x00 ch. 18.8 , page 74 tl1 0x8b 0x00 ch. 18.8 , page 74 tl2 0xcc 0x00 ch. 18.8 , page 74 tmod 0x89 0x00 table 65 , page 74 table 62 special function register reset values and description, alphabetically.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 72 of 104 june 2004 table 63 lists the functions of the bits in the psw register. bit function psw.7 cy - carry flag. set to 1 when last arithmetic operation resulted in a carry (during addition) or borrow (during subtraction); otherwise cleared to 0 by all arithmetic operations. psw.6 ac - auxiliary carry flag. set to 1 when last arithmetic operation resulted in a carry into (during addition) or borrow from (during subtraction) the high-order nibble; otherwise cleared to 0 by all arithmetic operations. psw.5 f0 - user flag 0. bit-addressable, general purpose flag for software control. psw.4 rs1 - register bank select bit 1. used with rs0 to select a register blank in internal ram. psw.3 rs0 - register bank select bit 0, decoded as: rs1 rs0 bank selected 0 0 register bank 0, addresses 0x00-0x07 0 1 register bank 1, addresses 0x08-0x0f 1 0 register bank 2, addresses 0x10-0x17 1 1 register bank 3, addresses 0x18-0x1f psw.2 ov - overflow flag. set to 1 when last arithmetic operation resulted in a carry (addition), borrow (subtraction), or overflow (multiply or divide); otherwise cleared to 0 by all arithmetic operations. psw.1 f1 - user flag 1. bit-addressable, general purpose flag for software control. psw.0 p - parity flag. set to 1 when modulo-2 sum of 8 bits in accumulator is 1 (odd parity); cleared to 0 on even parity. table 63 psw register ? sfr 0xd0.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 73 of 104 june 2004 18.7 sfr registers unique to nrf9e5 the table below lists the sfr registers that are unique to nrf9e5 (not part of standard 8051 register map) the registers p0, p1 and p2 (radio) use the addresses for the ports p0, p1 and p2 in a standard 8051. whereas the functionality of these ports is similar to that of the corresponding ports in standard 8051, it is not identical. addr sfr r/w #bit init hex name function 80 * r/w 8 ff p0 port 0, pins p07 to p00 90* r/w 8(4) ff p1** port 1, pins spi_csn, spi_miso, spi_mosi and spi_sck 94 r/w 8 ff p0_dir direction of each gpio bit of port 0 95 r/w 8 00 p0_alt select alternate functions for each pin of port 0 96 r/w 8(4) f4 p1_dir direction for each gpio bit of port 1 97 r/w 8(4) 00 p1_alt select alternate functions for each pin of port 1 a0* r/w 8 08 p2 general purpose io for interface to nrf905 radio, for details see chapter 8.1 a9 r/w 8 0 pwmcon pwm control register aa r/w 8 0 pwmduty pwm duty cycle ab r/w 8 0 regx_msb high part of 16 bit register for interface to watchdog and rtc ac r/w 8 0 regx_lsb low part of 16 bit register for interface to watchdog and rtc ad r/w 5 0 regx_ctrl control of interface to watchdog and rtc. b1 r/w 2 02 rstreas reset status and control b2 r/w 8 0 spi_data spi data input/output b3 r/w 2 0 spi_ctrl 00 -> spi not used 01 -> connect to p1 10 or 11 -> connect to radio b4 r/w 2 0 spiclk divider from cpu clock to spi clock b5 r/w 8 1d tick_dv tick divider. b6 w 3 0 ck_ctrl clock control b7 r 4 0 test_mode test mode register. this register must always be 0 in normal mode. bf r/w 6 27 cklfcon control generation of 4 khz cklf fe r 8 00 hwrev silicon stepping table 64 sfr registers unique to nrf9e5. * this bit addressable register differs in usage from ?standard 8051 ** only 4 lower bits are meaningful in p1 and corresponding p1_dir and p1_alt
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 74 of 104 june 2004 18.8 timers/counters the nrf9e5 includes three timer/counters (timer 0, timer 1 and timer 2). each timer/counter can operate as either a timer with a clock rate based on the cpu clock , or as an event counter clocked by the t0 pin (timer 0), t1 pin (timer 1), or the t2 pin (timer 2). these pins are alternate function bits of port 0 and 1 as this : t0 is p0.5, t1 is p0.6 and t2 is p1.0, for details please see ch. 6.3 on page 15 . each timer/counter consists of a 16-bit register that is accessible to software as three sfrs: ( table 61 ) timer 0 - tl0 and th0 timer 1 - tl1 and th1 timer 2 - tl2 and th2 18.8.1 timers 0 and 1 timers 0 and 1 each operate in four modes, as controlled through the tmod sfr ( table 65 ) and the tcon sfr ( table 66 ). the four modes are: - 13-bit timer/counter (mode 0) - 16-bit timer/counter (mode 1) - 8-bit counter with auto-reload (mode 2) - two 8-bit counters (mode 3, timer 0 only) bit function tmod.7 gate - timer 1 gate control. when gate = 1, timer 1 will clock only when external interrupt int1_n = 1 and tr1 (tcon.6) = 1. when gate = 0, timer 1 will clock only when tr1 = 1, regardless of the state of int1_n. tmod.6 c/t - counter/timer select. when c/t = 0, timer 1 is clocked by cpu_clk/4 or cpu_clk/12, depending on the state of t1m (ckcon.4). when c/t = 1, timer 1 is clocked by the t1 pin. tmod.5 m1 - timer 1 mode select bit 1. tmod.4 m0 - timer 1 mode select bit 0, decoded as: m1 m0 mode 00 mode 0 : 13-bit counter 01 mode 1 : 16-bit counter 10 mode 2 : 8-bit counter with auto-reload 11 mode 3 : two 8-bit counters tmod.3 gate - timer 0 gate control. when gate = 1, timer 0 will clock only when external interrupt int0_n = 1 and tr0 (tcon.4) = 1. when gate = 0, timer 0 will clock only when tr0 = 1, regardless of the state of int0_n. tmod.2 c/t - counter/timer select. when c/t = 0, timer 0 is clocked by cpu_clk/4 or cpu_clk/12, depending on the state of t0m (ckcon.3). when c/t = 1, timer 0 is clocked by the t0 pin. tmod.1 m1 - timer 0 mode select bit 1. tmod.0 m0 - timer 0 mode select bit 0, decoded as: m1 m0 mode 00 mode 0 : 13-bit counter 01 mode 1 : 16-bit counter 10 mode 2 : 8-bit counter with auto-reload 11 mode 3 : two 8-bit counters table 65 tmod register ? sfr 0x89.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 75 of 104 june 2004 bit function tcon.7 tf1 - timer 1 overflow flag. set to 1 when the timer 1 count overflows and cleared when the cpu vectors to the interrupt service routine. tcon.6 tr1 - timer 1 run control. set to 1 to enable counting on timer 1. tcon.5 tf0 - timer 0 overflow flag. set to 1 when the timer 0 count overflows and cleared when the cpu vectors to the interrupt service routine. tcon.4 tr0 - timer 0 run control. set to 1 to enable counting on timer 0. tcon.3 ie1 - interrupt 1 edge detect. if external interrupt 1 is configured to be edge-sensitive (it1 = 1), ie1 is set by hardware when a negative edge is detected on the int1_n external interrupt pin and is automatically cleared when the cpu vectors to the corresponding interrupt service routine. in edge-sensitive mode, ie1 can also be cleared by software. if external interrupt 1 is configured to be level-sensitive (it1 = 0), ie1 is set when the int1_n pin is low and cleared when the int1_n pin is high. in level-sensitive mode, software cannot write to ie1. tcon.2 it1 - interrupt 1 type select. when it1 = 1, the nrf9e5 detects external interrupt pin int1_n on the falling edge (edge-sensitive). when it1 = 0, the nrf9e5 detects int1_n as a low level (level-sensitive). tcon.1 ie0 - interrupt 0 edge detect. if external interrupt 0 is configured to be edge-sensitive (it0 = 1), ie0 is set by hardware when a negative edge is detected on the int0_n external interrupt pin and is automatically cleared when the cpu vectors to the corresponding interrupt service routine. in edge-sensitive mode, ie0 can also be cleared by software. if external interrupt 0 is configured to be level-sensitive (it0 = 0), ie0 is set when the int0_n pin is low and cleared when the int0_n pin is high. in level-sensitive mode, software cannot write to ie0. tcon.0 it0 - interrupt 0 type select. when it1 = 1, the nrf9e5 detects external interrupt int0_n on the falling edge (edge-sensitive). when it1 = 0, the nrf9e5 detects int0_n as a low level (level-sensitive). table 66 tcon register ? sfr 0x88. 18.8.1.1 mode 0 mode 0 operation, illustrated in figure 18 , is the same for timer 0 and timer 1. in mode 0, the timer is configured as a 13-bit counter that uses bits 0?4 of tl0 (or tl1) and all eight bits of th0 (or th1). the timer enable bit (tr0/tr1) in the tcon sfr starts the timer. the c/t bit selects the timer/counter clock source, cpu_clk or t0/t1. the timer counts transitions from the selected source as long as the gate bit is 0, or the gate bit is 1 and the corresponding interrupt pin (int0_n or int1_n) is deasserted. int0_n and int1_n are alternate function bits of port0, please see table 8 port functions . when the 13-bit count increments from 0x1fff (all ones), the counter rolls over to all zeros, the tf0 (or tf1) bit is set in the tcon sfr, and the t0_out (or t1_out) pin goes high for one clock cycle. the upper three bits of tl0 (or tl1) are indeterminate in mode 0 and must be masked when the software evaluates the register. 18.8.1.2 mode 1 mode 1 operation is the same for timer 0 and timer 1. in mode 1, the timer is configured as a 16-bit counter. as illustrated in, all eight bits of the lsb register (tl0 or tl1) are used. the counter rolls over to all zeros when the count increments from 0xffff. otherwise, mode 1 operation is the same as mode 0.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 76 of 104 june 2004 divide by 12 divide by 4 cpu_clk 0 1 0 1 p05/t0 (p06/t1) t0m (t1m) c/t tr0 (tr1) gate p0_alt.3 (p0_alt.4) p03/int0_n (p04/int1_n) clk tf0 (tf1) int 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 mode 0 mode 1 tl0 (tl1) th0 (th1) to serial port (timer 1 only) figure 18 timer 0/1 ? modes 0 and 1. 18.8.1.3 mode 2 mode 2 operation is the same for timer 0 and timer 1. in mode 2, the timer is configured as an 8-bit counter, with automatic reload of the start value. the lsb register (tl0 or tl1) is the counter, and the msb register (th0 or th1) stores the reload value. as illustrated in figure 19 timer 0/1 ? mode 2 , mode 2 counter control is the same as for mode 0 and mode 1. however, in mode 2, when tl n increments from 0xff, the value stored in th n is reloaded into tln. divide by 12 divide by 4 cpu_clk 0 1 0 1 p05/t0 (p06/t1) t0m (t1m) c/t tr0 (tr1) gate p0_alt.3 (p0_alt.4) p03/int0_n (p04/int1_n) clk tf0 (tf1) int 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 tl0 (tl1) th0 (th1) to serial port (timer 1 only) reload figure 19 timer 0/1 ? mode 2.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 77 of 104 june 2004 18.8.1.4 mode 3 in mode 3, timer 0 operates as two 8-bit counters, and timer 1 stops counting and holds its value. as shown in figure 20 timer 0 ? mode 3 , tl0 is configured as an 8-bit counter controlled by the normal timer 0 control bits. tl0 can count either cpu clock cycles (divided by 4 or by 12) or high-to-low transitions on t0, as determined by the c/t bit. the gate function can be used to give counter enable control to the int0_n signal. divide by 12 divide by 4 cpu_clk 0 1 0 1 p05/t0 t0m c/t tr0 gate p0_alt.3 p03/int0_n clk tf0 int 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 tl0 th0 tf1 int clk tr1 figure 20 timer 0 ? mode 3. th0 functions as an independent 8-bit counter. however, th0 can count only cpu clock cycles (divided by 4 or by 12). the timer 1 control and flag bits (tr1 and tf1) are used as the control and flag bits for th0. when timer 0 is in mode 3, timer 1 has limited usage because timer 0 uses the timer 1 control bit (tr1) and interrupt flag (tf1). timer 1 can still be used for baud rate generation and the timer 1 count values are still available in the tl1 and th1 registers.control of timer 1 when timer 0 is in mode 3 is through the timer 1 mode bits. to turn timer 1 on, set timer 1 to mode 0, 1, or 2. to turn timer 1 off, set it to mode 3. the timer 1 c/t bit and t1m bit are still available to timer 1. therefore, timer 1 can count cpu_clk/4, cpu_clk/12, or high-to-low transitions on the t1 pin. the timer 1 gate function is also available when timer 0 is in mode 3. 18.8.2 timer rate control the default timer clock scheme for the nrf9e5 timers is twelve cpu clock cycles per increment, the same as in the standard 8051. however, in the nrf9e5, the instruction cycle is four clock cycles. using the default rate (twelve clocks per timer increment) allows existing application code with real-time dependencies, such as baud rate, to operate properly. however, applications that require fast timing can set the timers to increment every four clock cycles by setting bits in the clock control register (ckcon) at sfr location 0x8e, described in table 67 ckcon register ? sfr 0x . the ckcon bits that control the timer clock rates are: ckcon bit counter/timer 5 timer 2 4 timer 1 3 timer 0 when a ckcon register bit is set to 1, the associated counter increments at four-clock intervals. when a ckcon bit is cleared, the associated counter increments at twelve- clock intervals. the timer controls are independent of each other. the default setting for
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 78 of 104 june 2004 all three timers is 0; that is, twelve-clock intervals. these bits have no effect in counter mode. bit function ckcon.7,6 reserved ckcon.5 t2m ? timer 2 clock select. when t2m = 0, timer 2 uses cpu_clk/12 (for compatibility with 80c32); when t2m = 1, timer 2 uses cpu_clk/4. this bit has no effect when timer 2 is configured for baud rate generation. ckcon.4 t1m ? timer 1 clock select. when t1m = 0, timer 1 uses cpu_clk/12 (for compatibility with 80c32); when t1m = 1, timer 1 uses cpu_clk/4. ckcon.3 t0m ? timer 0 clock select. when t0m = 0, timer 0 uses cpu_clk/12 (for compatibility with 80c32); when t0m = 1, timer 0 uses cpu_clk/4. ckcon.2? 0 md2, md1, md0 ? control the number of cycles to be used for external movx instructions; number of cycles is 2 + { md2, md1, md0} table 67 ckcon register ? sfr 0x8e. default initial data value is 0x01, i.e. movx takes 3 cycles. 18.8.3 timer 2 timer 2 runs only in 16-bit mode and offers several capabilities not available with timers 0 and 1. the modes available with timer 2 are: - 16-bit timer/counter - 16-bit timer with capture - 16-bit auto-reload timer/counter - baud-rate generator the sfrs associated with timer 2 are: - t2con ? sfr 0xc8; refer to table 68 t2con register ? sfr 0x - rcap2l ? sfr 0xca ? used to capture the tl2 value when timer 2 is configured for capture mode, or as the lsb of the 16-bit reload value when timer 2 is configured for auto-reload mode. - rcap2h ? sfr 0xcb ? used to capture the th2 value when timer 2 is configured for capture mode, or as the msb of the 16-bit reload value when timer 2 is configured for auto-reload mode. tl2 ? sfr 0xcc ? lower eight bits of the 16-bit count. th2 ? sfr 0xcd ? upper eight bits of the 16-bit count.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 79 of 104 june 2004 bit function t2con.7 tf2 - timer 2 overflow flag. hardware will set tf2 when timer 2 overflows from 0xffff. tf2 must be cleared to 0 by the software. tf2 will only be set to a 1 if rclk and tclk are both cleared to 0. writing a 1 to tf2 forces a timer 2 interrupt if enabled. t2con.6 exf2 - timer 2 external flag. hardware will set exf2 when a reload or capture is caused by a high-to-low transition on the t2ex pin, and exen2 is set. exf2 must be cleared to 0 by the software. writing a 1 to exf2 forces a timer 2 interrupt if enabled. t2con.5 rclk - receive clock flag. determines whether timer 1 or timer 2 is used for serial port timing of received data in serial mode 1 or 3. rclk = 1 selects timer 2 overflow as the receive clock. rclk = 0 selects timer 1 overflow as the receive clock. t2con.4 tclk - transmit clock flag. determines whether timer 1 or timer 2 is used for serial port timing of transmit data in serial mode 1 or 3. tclk =1 selects timer 2 overflow as the transmit clock. tclk = 0 selects timer 1 overflow as the transmit clock. t2con.3 exen2 - timer 2 external enable. exen2 = 1 enables capture or reload to occur as a result of a high-to-low transition on t2ex, if timer 2 is not generating baud rates for the serial port. exen2 = 0 causes timer 2 to ignore all external events at t2ex. t2con.2 tr2 - timer 2 run control flag. tr2 = 1 starts timer 2. tr2 = 0 stops timer 2. t2con.1 c/t2 - counter/timer select. c/t2 = 0 selects a timer function for timer 2. c/t2 = 1 selects a counter of falling transitions on the t2 pin. when used as a timer, timer 2 runs at four clocks per increment or twelve clocks per increment as programmed by ckcon.5, in all modes except baud-rate generator mode. when used in baud-rate generator mode, timer 2 runs at two clocks per increment, independent of the state of ckcon.5. t2con.0 cp/rl2 - capture/reload flag. when cp/rl2 = 1, timer 2 captures occur on high-to-low transitions of t2ex, if exen2 = 1. when cp/rl2 = 0, auto-reloads occur when timer 2 overflows or when high-to-low transitions occur on t2ex, if exen2 = 1. if either rclk or tclk is set to 1, cp/rl2 will not function, and timer 2 will operate in auto-reload mode following each overflow. table 68 t2con register ? sfr 0xc8. 18.8.3.1 timer 2 mode control table 69 summarizes how the sfr bits determine the timer 2 mode. rclk tclk cp/rl2 tr2 mode 0 0 1 1 16-bit timer/counter with capture 0 0 0 1 16-bit timer/counter with auto-reload 1 x x 1 baud-rate generator x 1 x 1 baud-rate generator x x x 0 off table 69 timer 2 mode control summary. 18.8.3.2 16-bit timer/counter mode figure 21 timer 2 ? timer/counter with capture illustrates how timer 2 operates in timer/counter mode with the optional capture feature. the c/t2 bit determines whether the 16-bit counter counts clock cycles (divided by 4 or 12), or high-to-low transitions on the t2 pin. the tr2 bit enables the counter. when the count increments from 0xffff, the tf2 flag is set, and t2_out goes high for one clock cycle.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 80 of 104 june 2004 divide by 12 divide by 4 cpu_clk 0 1 0 1 sck/t2 t2m c/t2 tr2 clk tf2 int tl2 capture 0 7 th2 8 15 rcap2l 0 7 rcap2h 8 15 exf2 divide by 2 exen2 lp_osc figure 21 timer 2 ? timer/counter with capture. 18.8.3.3 16-bit timer/counter mode with capture the timer 2 capture mode, illustrated in figure 21 timer 2 ? timer/counter with capture , is the same as the 16-bit timer/counter mode, with the addition of the capture registers and control signals. the cp/rl2 bit in the t2con sfr enables the capture feature. when cp/rl2 = 1, a high-to-low transition on t2ex when exen2 = 1 causes the timer 2 value to be loaded into the capture registers (rcap2l and rcap2h). 18.8.3.4 16-bit timer/counter mode with auto-reload when cp/rl2 = 0, timer 2 is configured for the auto-reload mode illustrated in figure 22 timer 2 ? timer/counter with auto-reload . control of counter input is the same as for the other 16-bit counter modes. when the count increments from 0xffff, timer 2 sets the tf2 flag and the starting value is reloaded into tl2 and th2. the software must preload the starting value into the rcap2l and rcap2h registers. when timer 2 is in auto-reload mode, a reload can be forced by a high-to-low transition on the t2ex pin, if enabled by exen2 = 1. divide by 12 divide by 4 cpu_clk 0 1 0 1 sck/t2 t2m c/t2 tr2 clk tf2 int tl2 reload 0 7 th2 8 15 rcap2l 0 7 rcap2h 8 15 exf2 divide by 2 exen2 lp_osc figure 22 timer 2 ? timer/counter with auto-reload.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 81 of 104 june 2004 18.8.3.5 baud rate generator mode setting either rclk or tclk to 1 configures timer 2 to generate baud rates for serial port in serial mode 1 or 3. in baud-rate generator mode, timer 2 functions in auto-reload mode. however, instead of setting the tf2 flag, the counter overflow generates a shift clock for the serial port function. as in normal auto-reload mode, the overflow also causes the preloaded start value in the rcap2l and rcap2h registers to be reloaded into the tl2 and th2 registers. when either tclk = 1 or rclk = 1, timer 2 is forced into auto-reload operation, regardless of the state of the cp/rl2 bit. when operating as a baud rate generator, timer 2 does not set the tf2 bit. in this mode, a timer 2 interrupt can be generated only by a high-to-low transition on the t2ex pin setting the exf2 bit, and only if enabled by exen2 = 1.the counter time base in baud- rate generator mode is cpu_clk/2. to use an external clock source, set c/t2 to 1 and apply the desired clock source to the t2 pin. divide by 2 cpu_clk 0 1 sck/t2 c/t2 tr2 clk int tl2 0 7 th2 8 15 rcap2l 0 7 rcap2h 8 15 exf2 divide by 2 exen2 lp_osc rclk 0 1 tclk 0 1 divide by 16 divide by 16 tx clock rx clock divide by 2 0 1 timer 1 overflow smod0 reload figure 23 timer 2 ? baud rate generator mode. 18.9 serial interface the nrf9e5 is configured with one serial port, which is identical in operation to the standard 8051 serial port. the two serial port pins rxd and txd are available as alternate functions of p0.1 and p0.2, for details please see ch. 6.3 on page 15 . the serial port can operate in synchronous or asynchronous mode. in synchronous mode, the nrf9e5 generates the serial clock and the serial port operates in half-duplex mode. in asynchronous mode, the serial port operates in full-duplex mode. in all modes, the nrf9e5 buffers receive data in a holding register, enabling the uart to receive an incoming word before the software has read the previous value. the serial port can operate in one of four modes, as outlined in table 70 .
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 82 of 104 june 2004 mode sync/as ync baud clock data bits start/ stop 9th bit function 0 sync cpu_clk/4 or cpu_clk/12 8 none none 1 async timer 1 or timer 2 8 1 start, 1 stop none 2 async cpu_clk/32 or cpu_clk/64 9 1 start, 1 stop 0, 1, parity 3 async timer 1 or timer 2 9 1 start, 1 stop 0, 1, parity table 70 serial port modes. the sfrs associated with the serial port are: - scon ? sfr 0x98 ? serial port control ( table 71 ) - sbuf ? sfr 0x99 ? serial port buffer bit function scon.7 sm0 - serial port mode bit 0. scon.6 sm1 - serial port mode bit 1, decoded as: sm0 sm1 mode 0 0 0 0 1 1 1 0 2 1 1 3 scon.5 sm2 - multiprocessor communication enable. in modes 2 and 3, sm2 enables the multiprocessor communication feature. if sm2 = 1 in mode 2 or 3, ri will not be activated if the received 9 th bit is 0. if sm2 = 1 in mode 1, ri will be activated only if a valid stop is received. in mode 0, sm2 establishes the baud rate: when sm2 = 0, the baud rate is cpu_clk/12; when sm2 = 1, the baud rate is cpu_clk/4. scon.4 ren - receive enable. when ren = 1, reception is enabled. scon.3 tb8 - defines the state of the 9 th data bit transmitted in modes 2 and 3. scon.2 rb8 - in modes 2 and 3, rb8 indicates the state of the 9 th bit received. in mode 1, rb8 indicates the state of the received stop bit. in mode 0, rb8 is not used. scon.1 ti - transmit interrupt flag. indicates that the transmit data word has been shifted out. in mode 0, ti is set at the end of the 8 th data bit. in all other modes, ti is set when the stop bit is placed on the txd pin. ti must be cleared by the software. table 71 scon register ? sfr 0x98. 18.9.1 mode 0 serial mode 0 provides synchronous, half-duplex serial communication. for serial port 0, both serial data input and output occur on rxd pin, and txd provides the shift clock for both transmit and receive. the rxd and txd pins are alternate function bits of port 0, please also see table 9 port 0 (p0) functions for port and pin configuration. the lack of open drain ports on nrf9e5 makes it a programmer responsibility to control the direction of the rxd pin.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 83 of 104 june 2004 the serial mode 0 baud rate is either cpu_clk/12 or cpu_clk/4, depending on the state of the sm2. when sm2 = 0, the baud rate is cpu_clk/12; when sm2 = 1, the baud rate is cpu_clk/4. mode 0 operation is identical to the standard 8051. data transmission begins when an instruction writes to the sbuf sfr. the uart shifts the data out, lsb first, at the selected baud rate, until the 8-bit value has been shifted out. mode 0 data reception begins when the ren bit is set and the ri bit is cleared in the corresponding scon sfr. the shift clock is activated and the uart shifts data in on each rising edge of the shift clock until eight bits have been received. one machine cycle after the 8 th bit is shifted in, the ri bit is set and reception stops until the software clears the ri bit. figure 24 serial port mode 0 receive timing for low-speed (cpu_clk/12) operation. figure 25 serial port mode 0 receive timing for high-speed (cpu_clk/4) operation. : figure 26 serial port mode 0 transmit timing for high-speed (cpu_clk/4) operation. : figure 27 serial port mode 0 transmit timing for high-speed (cpu_clk/4) operation.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 84 of 104 june 2004 18.9.2 mode 1 mode 1 provides standard asynchronous, full-duplex communication, using a total of ten bits: one start bit, eight data bits, and one stop bit. for receive operations, the stop bit is stored in rb8. data bits are received and transmitted lsb first. 18.9.2.1 mode 1 baud rate the mode 1 baud rate is a function of timer overflow. serial port can use either timer 1 or timer 2 to generate baud rates. each time the timer increments from its maximum count (0xff for timer 1 or 0xffff for timer 2), a clock is sent to the baud-rate circuit. the clock is then divided by 16 to generate the baud rate. when using timer 1, the smod bit selects whether or not to divide the timer 1 rollover rate by 2. therefore, when using timer 1, the baud rate is determinedby the equation: baud rate = 32 2 smod x timer 1 overflow smod is sfr bit pcon.7 when using timer 2, the baud rate is determined by the equation: baud rate = 16 overflow 2 timer to use timer 1 as the baud-rate generator, it is best to use timer 1 mode 2 (8-bit counter with auto-reload), although any counter mode can be used. the timer 1 reload value is stored in the th1 register, which makes the complete formula for timer 1: baud rate = 32 2 smod x th1) - (256 x 4 clk the 4 in the denominator in the above equation can be obtained by setting the t1m bit in the ckcon sfr. to derive the required th1 value from a known baud rate (when tm1 = 0), use the equation: th1 = 256 - rate baud 128 2 * * clk smod you can also achieve very low serial port baud rates from timer 1 by enabling the timer 1 interrupt, configuring timer 1 to mode 1, and using the timer 1 interrupt to initiate a 16-bit software reload. table table 72 lists sample reload values for a variety of common serial port baud rates.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 85 of 104 june 2004 desired baud rate smod c/t timer 1 mode th1 value for 16 mhz cpu clk th1 value for 8 mhz cpu clk 19.2 kb/s 1 0 2 0xf3 - 9.6 kb/s 1 0 2 0xe6 0xf3 4.8 kb/s 1 0 2 0xcc 0xe6 0.4 kb/s 1 0 2 0x98 0xcc 1.2 kb/s 1 0 2 0x30 0x98 table 72 timer 1 reload values for serial port mode 1 baud rates. to use timer 2 as the baud-rate generator, configure timer 2 in auto-reload mode and set the tclk and/or rclk bits in the t2con sfr. tclk selects timer 2 as the baud- rate generator for the transmitter; rclk selects timer 2 as the baud-rate generator for the receiver. the 16-bit reload value for timer 2 is stored in the rcap2l and rca2h sfrs, which makes the equation for the timer 2 baud rate: baud rate = rcap2l}) {rcap2h, - (65536 x 32 clk where rcap2h,rcap2l is the content of rcap2h and rcap2l taken as a 16-bit unsigned number. the 32 in the denominator is the result of the cpu_clk signal being divided by 2 and the timer 2 overflow being divided by 16. setting tclk or rclk to 1 automatically causes the cpu_clk signal to be divided by 2, as shown in figure 23 timer 2 ? baud rate generator mode , instead of the 4 or 12 determined by the t2m bit in the ckcon sfr. to derive the required rcap2h and rcap2l values from a known baud rate, use the equation: rcap2h,rcap2l = 65536 ? rate baud x 32 clk table table 73 lists sample values of rcap2l and rcap2h for a variety of desired baud rates. 16 mhz cpu clk baud rate c/t 2 rcap2h rcap2l 57.6 kb/s 0 0xff 0xf7 19.2 kb/s 0 0xff 0xe6 9.6 kb/s 0 0xff 0xcc 4.8 kb/s 0 0xff 0x98 0.4 kb/s 0 0xff 0x30 1.2 kb/s 0 0xfe 0x5f table 73 timer 2 reload values for serial port mode 1 baud rates. when either rclk or tclk is set, the tf2 flag will not be set on a timer 2 rollover, and the t2ex reload trigger is disabled.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 86 of 104 june 2004 18.9.2.2 mode 1 transmit figure 28 illustrates the mode 1 transmit timing. in mode 1, the uart begins transmitting after the first rollover of the divide-by-16 counter after the software writes to the sbuf register. the uart transmits data on the txd pin in the following order: start bit, eight data bits (lsb first), stop bit. the ti bit is set two clock cycles after the stop bit is transmitted. figure 28 serial port mode 1 transmit timing. 18.9.2.3 mode 1 receive figure 29 illustrates the mode 1 receive timing. reception begins at the falling edge of a start bit received on rxd_in, when enabled by the ren bit. for this purpose, rxd_in is sampled sixteen times per bit for any baud rate. when a falling edge of a start bit is detected, the divide-by-16 counter used to generate the receive clock is reset to align the counter rollover to the bit boundaries. figure 29 serial port mode 1 receive timing.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 87 of 104 june 2004 for noise rejection, the serial port establishes the content of each received bit by a majority decision of three consecutive samples in the middle of each bit time. this is especially true for the start bit. if the falling edge on rxd_in is not verified by a majority decision of three consecutive samples (low), then the serial port stops reception and waits for another falling edge on rxd_in. at the middle of the stop bit time, the serial port checks for the following conditions: - ? ri = 0 - if sm2 = 1, the state of the stop bit is 1 (if sm2 = 0, the state of the stop bit does not matter) if the above conditions are met, the serial port then writes the received byte to the sbuf register, loads the stop bit into rb8, and sets the ri bit. if the above conditions are not met, the received data is lost, the sbuf register and rb8 bit are not loaded, and the ri bit is not set. after the middle of the stop bit time, the serial port waits for another high- to-low transition on the rxd_in pin. mode 1 operation is identical to that of the standard 8051 when timers 1 and 2 use cpu_clk/12 (the default). 18.9.3 mode 2 mode 2 provides asynchronous, full-duplex communication, using a total of eleven bits: - one start bit - eight data bits - one programmable 9th bit - one stop bit the data bits are transmitted and received lsb first. for transmission, the 9th bit is determined by the value in tb8. to use the 9th bit as a parity bit, move the value of the p bit (sfr psw.0) to tb8. the mode 2 baud rate is either cpu_clk/32 or cpu_clk/64, as determined by the smod bit. the formula for the mode 2 baud rate is: baud rate = 64 2 clk smod * mode 2 operation is identical to the standard 8051. 18.9.3.1 mode 2 transmit figure 30 illustrates the mode 2 transmit timing. transmission begins after the first rollover of the divide-by-16 counter following a software write to sbuf . the uart shifts data out on the txd pin in the following order: start bit, data bits (lsb first), 9th bit, stop bit. the ti bit is set when the stop bit is placed on the txd pin.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 88 of 104 june 2004 figure 30 serial port mode 2 transmit timing.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 89 of 104 june 2004 18.9.3.2 mode 2 receive figure 31 illustrates the mode 2 receive timing. reception begins at the falling edge of a start bit received on rxd_in, when enabled by the ren bit. for this purpose, rxd_in is sampled sixteen times per bit for any baud rate. when a falling edge of a start bit is detected, the divide-by-16 counter used to generate the receive clock is reset to align the counter rollover to the bit boundaries. figure 31 serial port mode 2 receive timing. for noise rejection, the serial port establishes the content of each received bit by a majority decision of three consecutive samples in the middle of each bit time. this is especially true for the start bit. if the falling edge on rxd_in is not verified by a majority decision of three consecutive samples (low), then the serial port stops reception and waits for another falling edge on rxd_in. at the middle of the stop bit time, the serial port checks for the following conditions: - ri = 0 - if sm2 = 1, the state of the stop bit is 1 (if sm2 = 0, the state of the stop bit does not matter) if the above conditions are met, the serial port then writes the received byte to the sbuf register, loads the 9th received bit into rb8, and sets the ri bit. if the above conditions are not met, the received data is lost, the sbuf register and rb8 bit are not loaded, and the ri bit is not set. after the middle of the stop bit time, the serial port waits for another high-to-low transition on the rxd_in. 18.9.4 mode 3 mode 3 provides asynchronous, full-duplex communication, using a total of eleven bits: - one start bit - eight data bits - one programmable 9th bit - one stop bit; the data bits are transmitted and received lsb first the mode 3 transmit and receive operations are identical to mode 2. the mode 3 baud rate generation is identical to mode 1. that is, mode 3 is a combination of mode 2 protocol and mode 1 baud rate. figure 32 illustrates the mode 3 transmit timing. mode 3 operation is identical to that of the standard 8051 when timers 1 and 2 use cpu_clk/12 (the default).
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 90 of 104 june 2004 figure 32 serial port mode 3 transmit timing. figure 33 illustrates the mode 3 receive timing. figure 33 serial port mode 3 receive timing.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 91 of 104 june 2004 18.9.5 multiprocessor communications the multiprocessor communication feature is enabled in modes 2 and 3 when the sm2 bit is set in the scon sfr for a serial port. in multiprocessor communication mode, the 9th bit received is stored in rb8 and, after the stop bit is received, the serial port interrupt is activated only if rb8 = 1. a typical use for the multiprocessor communication feature is when a master wants to send a block of data to one of several slaves. the master first transmits an address byte that identifies the target slave. when transmitting an address byte, the master sets the 9 th bit to 1; for data bytes, the 9th bit is 0. when sm2 = 1, no slave will be interrupted by a data byte. however, an address byte interrupts all slaves so that each slave can examine the received address byte to determine whether that slave is being addressed. address decoding must be done by software during the interrupt service routine. the addressed slave clears its sm2 bit and prepares to receive the data bytes. the slaves that are not being addressed leave the sm2 bit set and ignore the incoming data bytes.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 92 of 104 june 2004 19 package outline nrf9e5 uses the qfn 32l 5x5 green package with a mat tin finish. dimensions are in mm. recommended soldering reflow profile can be found in application note nan400- 08, qfn soldering reflow guidelines, www.nordicsemi.no. + package type a a1 a2 b d e e j k l qfn32 (5x5 mm) min typ. max 0.8 0.9 0.0 0.05 0.65 0.69 0.18 0.23 0.3 5 bsc 5 bsc 0.5 bsc 3.2 3.3 3.4 3.2 3.3 3.4 0.3 0.4 0.5 figure 34 nrf9e5 package outline.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 93 of 104 june 2004 20 pcb layout and decoupling guidelines nrf9e5 is an extremely robust rf device due to internal voltage regulators and requires the minimum of rf layout protocols. however the following design rules should still be incorporated into the layout design. a pcb with a minimum of two layers including a ground plane is recommended for optimum performance. the nrf9e5 dc supply voltage should be decoupled as close as possible to the vdd pins with high performance rf capacitors. it is preferable to mount a large surface mount capacitor (e.g. 4.7 m f tantalum) in parallel with the smaller value capacitors. the nrf9e5 supply voltage should be filtered and routed separately from the supply voltages of any digital circuitry. long power supply lines on the pcb should be avoided. all device grounds, vdd connections and vdd bypass capacitors must be connected as close as possible to the nrf9e5 ic. for a pcb with a topside rf ground plane, the vss pins should be connected directly to the ground plane. for a pcb with a bottom ground plane, the best technique is to place via holes as close as possible to the vss pins. a minimum of one via hole should be used for each vss pin. full swing digital data or control signals should not be routed close to the crystal or the power supply lines. a fully qualified rf-layout for the nrf9e5 and its surrounding components, including antennas and matching networks, can be downloaded from www.nordicsemi.no.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 94 of 104 june 2004 21 application examples 21.1 differential connection to a loop antenna p01 1 vss 24 vss 18 vdd 17 vss 16 p02 2 p03 3 vdd 4 vss 5 p04 6 p05 7 p06 8 p07 9 mosi 10 miso 11 sck 12 xc2 15 xc1 14 eecsn 13 vdd_pa 19 ant1 20 ant2 21 vss 22 iref 23 nrf9e5 vdd 25 ain3 26 ain2 27 ain1 28 ain0 29 aref 30 dvdd_1v2 31 p00 32 u1 nrf9e5 c9 1nf r3 1k c10 100nf cs 1 so 2 wp 3 vss 4 si 5 sck 6 hold 7 vcc 8 u2 25xx320 c11 10nf r4 10k r5 100k vdd vdd c2 22pf c6 4.7nf c5 33pf r2 22k c7 10nf vdd c1 22pf r1 1m x1 16 mhz c8 33pf vdd mosi (p1.1) miso (p1.2) sck (p1.0) eecsn (p1.3) p00 p01 p02 p03 p04 p05 p06 p07 ain0 ain1 ain2 ain3 aref vdd c4 3.3nf 0603 c3 33pf r6 18k c13 4.7pf c14 5.6pf aaaaaaaa j1 loop antenna 9.5x9.5mm c12 3.9pf aaaaaaaa aaaaaaaa aaaaaaaa figure 35 nrf9e5 application schematic, differential connection to a loop antenna (868mhz) .
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 95 of 104 june 2004 component description size value tol. units c1 np0 ceramic chip capacitor, (crystal oscillator) 0603 22 5% pf c2 np0 ceramic chip capacitor, (crystal oscillator) 0603 22 5% pf c3 np0 ceramic chip capacitor, (pa supply decoupling) 0603 33 5% pf c4 x7r ceramic chip capacitor, (pa supply decoupling) 0603 3.3 10% nf c5 np0 ceramic chip capacitor, (supply decoupling) 0603 33 5% pf c6 x7r ceramic chip capacitor, (supply decoupling) 0603 4.7 10% nf c7 x7r ceramic chip capacitor, (supply decoupling) 0603 10 10% nf c8 np0 ceramic chip capacitor, (supply decoupling) 0603 33 5% pf c9 x7r ceramic chip capacitor, (aref filtering) 0603 1 10% nf c10 x7r ceramic chip capacitor, (aref filtering) 0603 100 10% nf c11 x7r ceramic chip capacitor 0603 10 10% nf c12 np0 ceramic chip capacitor, (antenna tuning) 0603 3.9 0.1 pf c13 np0 ceramic chip capacitor, (antenna tuning) 0603 4.7 0.1 pf c14 np0 ceramic chip capacitor, (antenna tuning) 0603 5.6 0.1 pf r1 0.1w chip resistor, (crystal oscillator bias) 0603 1 1% m w r2 0.1w chip resistor, (reference bias) 0603 22 1% k w r3 0.1w chip resistor 0603 1 1% k w r4 0.1w chip resistor 0603 10 1% k w r5 0.1w chip resistor 0603 100 1% k w r6 0.1w chip resistor, (antenna q reduction) 0603 18 1% k w u1 nrf9e5 transceiver qfn32l/5x5 u2 4 kbyte serial eeprom with spi interface so8 2xx320 x1 crystal (see chapter 7.1 ) lxwxh = 4.0x2.5x0.8 16 30ppm mhz table 74 recommended external components, differential connection to a loop antenna (868mhz) .
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 96 of 104 june 2004 21.2 pcb layout example, differential connection to a loop antenna figure 36 shows a pcb layout example for the application schematic in figure 35 . a double-sided fr-4 board of 1.6mm thickness is used. this pcb has a ground plane on the bottom layer. additionally, there are ground areas on the component side of the board to ensure sufficient grounding of critical components. a large number of via holes connect the top layer ground areas to the bottom layer ground plane. there is no ground plane beneath the antenna. a) top silk screen no components in bottom layer b) bottom silk screen c) top view d) bottom view figure 36 pcb layout example for nrf9e5, differential connection to a loop antenna.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 97 of 104 june 2004 21.3 single ended connection to 50 w antenna p01 1 vss 24 vss 18 vdd 17 vss 16 p02 2 p03 3 vdd 4 vss 5 p04 6 p05 7 p06 8 p07 9 mosi 10 miso 11 sck 12 xc2 15 xc1 14 eecsn 13 vdd_pa 19 ant1 20 ant2 21 vss 22 iref 23 nrf9e5 vdd 25 ain3 26 ain2 27 ain1 28 ain0 29 aref 30 dvdd_1v2 31 p00 32 u1 nrf9e5 c9 1nf r3 1k c10 100nf cs 1 so 2 wp 3 vss 4 si 5 sck 6 hold 7 vcc 8 u2 25xx320 c11 10nf r4 10k r5 100k vdd vdd c2 22pf c6 4.7nf c5 33pf r2 22k c7 10nf vdd c1 22pf r1 1m x1 16 mhz vdd l1 c3 c14 not fitted c15 l3 l2 c12 c13 c4 3.3nf c8 33pf vdd c16 c3 c12 c13 c14 c15 c16 l1 l2 l3 868/915mhz 433mhz 33pf, 5% 3.9pf, 0.25pf 3.9pf, 0.25pf not fitted not fitted 33pf, 5% not fitted 12nh, 5% 12nh, 5% 12nh, 5% 180pf, 5% 18pf, 5% 18pf, 5% 6.8pf, 5% not fitted 12nh, 5% 39nh, 5% 39nh, 5% mosi (p1.1) miso (p1.2) sck (p1.0) eecsn (p1.3) p00 p01 p02 p03 p04 p05 p06 p07 ain0 ain1 ain2 ain3 aref 50 ohm rf i/o aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa figure 37 nrf9e5 application schematic, single ended connection to 50 w antenna by using a differential to single ended matching network .
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 98 of 104 june 2004 component description size value tol. units c1 np0 ceramic chip capacitor, (crystal oscillator) 0603 22 5% pf c2 np0 ceramic chip capacitor, (crystal oscillator) 0603 22 5% pf c3 np0 ceramic chip capacitor, (pa supply decoupling) @ 433mhz @ 868 @ 915mhz 0603 180 33 33 5% pf c4 x7r ceramic chip capacitor, (pa supply decoupling) 0603 3.3 10% nf c5 np0 ceramic chip capacitor, (supply decoupling) 0603 33 5% pf c6 x7r ceramic chip capacitor, (supply decoupling) 0603 4.7 10% nf c7 x7r ceramic chip capacitor, (supply decoupling) 0603 10 10% nf c8 np0 ceramic chip capacitor, (supply decoupling) 0603 33 5% pf c9 x7r ceramic chip capacitor, (aref filtering) 0603 1 10% nf c10 x7r ceramic chip capacitor, (aref filtering) 0603 100 10% nf c11 x7r ceramic chip capacitor 0603 10 10% nf c12 np0 ceramic chip capacitor, (impedance matching) @ 433mhz @ 868 @ 915mhz 0603 18 3.9 3.9 5% < 0.25pf < 0.25pf pf c13 np0 ceramic chip capacitor, (impedance matching) @ 433mhz @ 868 @ 915mhz 0603 18 3.9 3.9 5% < 0.25pf < 0.25pf pf c14 np0 ceramic chip capacitor, (impedance matching) 0603 not fitted pf c15 np0 ceramic chip capacitor, (impedance matching) @ 433mhz @ 868 @ 915mhz 0603 6.8 33 33 5% 5% 5% pf c16 np0 ceramic chip capacitor, (impedance matching) @ 433mhz @ 868 @ 915mhz 0603 not fitted not fitted not fitted pf l1 chip inductor, (impedance matching) @ 433mhz: srf> 433mhz @ 868mhz: srf> 868mhz @ 915mhz: srf> 915mhz 0603 12 12 12 5% nh l2 chip inductor, (impedance matching) @ 433mhz: srf> 433mhz @ 868mhz: srf> 868mhz @ 915mhz: srf> 915mhz 0603 39 12 12 5% 5% 5% nh l3 chip inductor, (impedance matching) @ 433mhz: srf> 433mhz @ 868mhz: srf> 868mhz @ 915mhz: srf> 915mhz 0603 39 12 12 5% 5% 5% nh r1 0.1w chip resistor, (crystal oscillator bias) 0603 1 1% m w r2 0.1w chip resistor, (reference bias) 0603 22 1% k w r3 0.1w chip resistor 0603 1 1% k w r4 0.1w chip resistor 0603 10 1% k w r5 0.1w chip resistor 0603 100 1% k w u1 nrf9e5 transceiver qfn32l/5x5 u2 4 kbyte serial eeprom with spi interface so8 2xx320 x1 crystal (see chapter 7.1 ) lxwxh = 4.0x2.5x0.8 16 30ppm mhz table 75 recommended external components, s ingle ended connection to 50 w antenna .
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 99 of 104 june 2004 21.4 pcb layout example, single ended connection to 50 w antenna figure 38 shows a pcb layout example for the application schematic in figure 37 . a double-sided fr-4 board of 1.6mm thickness is used. this pcb has a ground plane on the bottom layer. additionally, there are ground areas on the component side of the board to ensure sufficient grounding of critical components. a large number of via holes connect the top layer ground areas to the bottom layer ground plane. a) top silk screen no components in bottom layer b) bottom silk screen c) top view d) bottom view figure 38 pcb layout example for nrf9e5, single ended connection to 50 w antenna by using a differential to single ended matching network. 21.5 configure the chip as nrf905. nrf9e5 is easily configurable as nrf905. upon power up the boot loader is run. if miso is set to low value during the first 10ms, the microcontroller configures itself to nrf905 mode. all pins are then defined as for the nrf905 chip.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 100 of 104 june 2004 22 absolute maximum ratings supply voltage vdd ............................... - 0.3v to + 3.6v vss ................................ ..................... 0v input voltage v i .......................... - 0.3v to vdd + 0.3v output voltage v o ......................... - 0.3v to vdd + 0.3v total power dissipation p d (t a =85 c) ................................ 230mw temperatures operating temperature ................................ ............ - 40 c to + 85 c storage temperature ................................ ............... - 40 c to + 125 c note: stress exceeding one or more of the limiting values may cause permanent damage to the device. attention! electrostatic sensitive device. observe precaution for handling.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 101 of 104 june 2004 23 glossery of terms term description adc analog to digital converter am address match bom bill of material cd carrier detect clk clock crc cyclic redundancy check csn spi chip select not dr data ready gfsk gaussian frequency shift keying gpio general purpose input output ism industrial-scientific-medical ksps kilo samples per second mcu micro controller unit miso spi master in slave out mosi spi master out slave in pwm pulse-width modulation pwr_dwn power down pwr_up power up ram random access memory rom read only memory rtc real time clock rx receive sck spi serial clock spi serial programmable interface stby standby trx_en transmit/receive enable tx transmit tx_en transmit enable uart universal asynchronous receiver transmitter xtal crystal table 76 glossary of terms.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 102 of 104 june 2004 24 definitions data sheet status objective product specification this datasheet contains target specifications for product development. preliminary product specification this datasheet contains preliminary data; supplementary data may be published from nordic semiconductor asa later. product specification this datasheet contains final product specifications. nordic semiconductor asa reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. limiting values stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the specifications sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the specification. table 77 definitions. nordic semiconductor asa reserves the right to make changes without further notice to the product to improve reliability, function or design. nordic semiconductor does not assume any liability arising out of the application or use of any product or circuits described herein. life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. nordic semiconductor asa customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify nordic semiconductorsemiconductor asa for any damages resulting from such improper use or sale. product specification revision date: 8.06.2004 datasheet order code: 080604nrf9e5 all rights reserved ?. reproduction in whole or in part is prohibited without the prior written permission of the copyright holder.
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 103 of 104 june 2004 25 your notes
product specification nrf 9 e5 single chip transceiver with embedded microcontroller and adc main office: nordic semiconductor asa - vestre rosten 81, n-7075 tiller, norway -phone +4772898900 - fax +4772898989 revision: 1.1 page 104 of 104 june 2004 nordic semiconductor asa ? world wide distributors for your nearest dealer, please see http://www.nordicsemi.no main office: vestre rosten 81, n-7075 tiller, norway phone: +47 72 89 89 00, fax: +47 72 89 89 89 visit the nordic semiconductor asa website at http://www.nordicsemi.no

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